Lines Matching refs:mcr
33 mcr p14, 0, \ch, c0, c5, 0
39 mcr p14, 0, \ch, c8, c0, 0
45 mcr p14, 0, \ch, c1, c0, 0
618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
619 mcr p15, 0, r0, c6, c7, 1
622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
639 mcr p15, 0, r0, c1, c0, 0 @ write control reg
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
652 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
655 mcr p15, 0, r0, c5, c0, 0 @ access permission
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
668 mcr p15, 0, r0, c1, c0, 0 @ write control reg
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
727 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
733 mcr p15, 7, r0, c15, c0, 0
742 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
762 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
784 mcr p15, 0, r0, c7, c5, 4 @ ISB
785 mcr p15, 0, r0, c1, c0, 0 @ load control register
788 mcr p15, 0, r0, c7, c5, 4 @ ISB
796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
797 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
798 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
803 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
812 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
813 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
816 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
1048 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1050 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1051 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1052 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1058 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1067 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1081 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1089 mcr p15, 0, r0, c7, c10, 4 @ DSB
1090 mcr p15, 0, r0, c7, c5, 4 @ ISB
1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1114 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1122 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1131 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1138 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1140 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1150 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1153 mcr p15, 0, r10, c7, c10, 5 @ DMB
1166 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1167 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1185 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1197 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1199 mcr p15, 0, r10, c7, c10, 4 @ DSB
1200 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1201 mcr p15, 0, r10, c7, c10, 4 @ DSB
1202 mcr p15, 0, r10, c7, c5, 4 @ ISB
1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1211 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1245 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3