Lines Matching refs:mov
59 mov \rb, #0x80000000 @ physical base address
75 mov r0, \val
80 mov r0, \val
81 mov r1, #\len
110 mov r0, r4
129 mov r0, r0
131 ARM( mov r0, r0 )
148 mov r7, r1 @ save architecture ID
149 mov r8, r2 @ save atags pointer
160 mov r0, #0x17 @ angel_SWIreason_EnterSVC
198 mov r4, pc
212 mov r0, pc
255 mov r10, r6
258 mov r5, #0 @ init dtb size to 0
304 mov r5, r5, ror #8
321 mov r0, r8
322 mov r1, r6
323 mov r2, r5
335 mov r1, r6
336 mov r2, r5
343 mov r8, r6 @ use the appended device tree
363 mov r5, r5, ror #8
452 mov pc, r0
515 not_relocated: mov r0, #0
539 mov r0, r4
540 mov r1, sp @ malloc space above stack
542 mov r3, r7
546 mov r1, r7 @ restore architecture number
547 mov r2, r8 @ restore atags pointer
586 mov pc, lr
609 cache_on: mov r3, #8 @ cache_on function
617 mov r0, #0x3f @ 4G, the whole
621 mov r0, #0x80 @ PR7
626 mov r0, #0xc000
630 mov r0, #0
641 mov r0, #0
644 mov pc, lr
647 mov r0, #0x3f @ 4G, the whole
650 mov r0, #0x80 @ PR7
654 mov r0, #0xc000
657 mov r0, #0
667 mov r0, #0
672 mov pc, lr
687 mov r0, r3
688 mov r9, r0, lsr #18
689 mov r9, r9, lsl #18 @ start of RAM
691 mov r1, #0x12 @ XN|U + section mapping
711 mov r2, pc
712 mov r2, r2, lsr #20
718 mov pc, lr
732 mov r0, #4 @ put dcache in WT mode
737 mov r12, lr
739 mov r6, #CB_BITS | 0x12 @ U
741 mov r0, #0
749 mov r0, #0
752 mov pc, r12
755 mov r12, lr
761 mov r0, #0
787 mov r0, #0
789 mov pc, r12
792 mov r12, lr
793 mov r6, #CB_BITS | 0x12 @ U
795 mov r0, #0
802 mov r0, #0
804 mov pc, r12
811 mov r1, #-1
882 mov pc, lr
884 mov pc, lr
886 mov pc, lr
891 mov pc, lr
893 mov pc, lr
895 mov pc, lr
902 mov pc, lr
925 mov pc, lr
927 mov pc, lr
929 mov pc, lr
1013 mov pc, lr
1015 mov pc, lr
1017 mov pc, lr
1042 cache_off: mov r3, #12 @ cache_off function
1049 mov r0, #0
1053 mov pc, lr
1059 mov r0, #0
1061 mov pc, lr
1068 mov r0, #0
1072 mov pc, lr
1082 mov r12, lr
1084 mov r0, #0
1091 mov pc, r12
1103 mov r3, #16
1109 mov r2, #1
1110 mov r3, #0
1112 mov r1, #7 << 5 @ 8 segments
1123 mov pc, lr
1128 mov r1, #0
1132 mov pc, lr
1135 mov r1, #0
1141 mov pc, lr
1148 mov r10, #0
1157 mov r3, r3, lsr #23 @ left align loc bit field
1159 mov r10, #0 @ start clean at cache level 0
1162 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1177 mov r9, r4 @ create working copy of max way size
1196 mov r10, #0 @ swith back to cache level 0
1203 mov pc, lr
1212 mov pc, lr
1217 mov r2, #64*1024 @ default: 32K dcache size (*2)
1218 mov r11, #32 @ default: 32 byte line size
1222 mov r1, r3, lsr #18
1224 mov r2, #1024
1225 mov r2, r2, lsl r1 @ base dcache size *2
1228 mov r3, r3, lsr #12
1230 mov r11, #8
1231 mov r11, r11, lsl r3 @ cache line size in bytes
1233 mov r1, pc
1246 mov pc, lr
1252 mov r1, #0
1254 mov pc, lr
1268 mov r2, #0
1274 mov r0, r0, lsr #4
1287 mov r1, #0x00020000
1295 mov pc, lr
1298 mov r2, r0
1299 mov r0, #0
1304 memdump: mov r12, r0
1305 mov r10, lr
1306 mov r11, #0
1307 2: mov r0, r11, lsl #2
1309 mov r1, #8
1311 mov r0, #':'
1313 1: mov r0, #' '
1316 mov r1, #8
1326 mov r0, #'\n'
1330 mov pc, r10
1349 mov r0, #0 @ must be 0
1350 ARM( mov pc, r4 ) @ call kernel