Lines Matching refs:clock
73 clock: clock-controller@10030000 { label
74 compatible = "samsung,exynos4412-clock";
76 #clock-cells = <1>;
84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85 clock-names = "fin_pll", "mct";
130 clocks = <&clock CLK_TSADC>;
131 clock-names = "adc";
153 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
155 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
156 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
157 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
158 <&clock CLK_XUSBXTI>;
159 #clock-cells = <1>;
166 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
167 clock-names = "sclk_fimg2d", "fimg2d";
172 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
173 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
174 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
215 clocks = <&clock CLK_FIMC_LITE0>;
216 clock-names = "flite";
225 clocks = <&clock CLK_FIMC_LITE1>;
226 clock-names = "flite";
235 clocks = <&clock CLK_FIMC_LITE0>,
236 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
237 <&clock CLK_PPMUISPMX>,
238 <&clock CLK_MOUT_MPLL_USER_T>,
239 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
240 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
241 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
242 <&clock CLK_DIV_MCUISP0>,
243 <&clock CLK_DIV_MCUISP1>,
244 <&clock CLK_UART_ISP_SCLK>,
245 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
246 <&clock CLK_ACLK400_MCUISP>,
247 <&clock CLK_DIV_ACLK400_MCUISP>;
248 clock-names = "lite0", "lite1", "ppmuispx",
267 clocks = <&clock CLK_I2C1_ISP>;
268 clock-names = "i2c_isp";
282 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
283 clock-names = "biu", "ciu";
297 clocks = <&clock 383>;
298 clock-names = "tmu_apbif";
308 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
309 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
310 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;