Lines Matching refs:clks
53 clocks = <&clks IMX5_CLK_ARM>;
119 clocks = <&clks IMX5_CLK_SATA_GATE>,
120 <&clks IMX5_CLK_SATA_REF>,
121 <&clks IMX5_CLK_AHB>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
204 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
205 <&clks IMX5_CLK_DUMMY>,
206 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
216 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
217 <&clks IMX5_CLK_UART3_PER_GATE>;
228 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
229 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
242 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
255 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
256 <&clks IMX5_CLK_DUMMY>,
257 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
267 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
268 <&clks IMX5_CLK_DUMMY>,
269 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
283 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
290 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
340 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
387 clocks = <&clks IMX5_CLK_DUMMY>;
395 clocks = <&clks IMX5_CLK_DUMMY>;
402 clocks = <&clks IMX5_CLK_DUMMY>;
410 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
411 <&clks IMX5_CLK_GPT_HF_GATE>;
431 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
432 <&clks IMX5_CLK_LDB_DI1_SEL>,
433 <&clks IMX5_CLK_IPU_DI0_SEL>,
434 <&clks IMX5_CLK_IPU_DI1_SEL>,
435 <&clks IMX5_CLK_LDB_DI0_GATE>,
436 <&clks IMX5_CLK_LDB_DI1_GATE>;
477 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
478 <&clks IMX5_CLK_PWM1_HF_GATE>;
487 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
488 <&clks IMX5_CLK_PWM2_HF_GATE>;
497 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
498 <&clks IMX5_CLK_UART1_PER_GATE>;
507 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
508 <&clks IMX5_CLK_UART2_PER_GATE>;
517 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
518 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
527 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
528 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
539 clks: ccm@53fd4000{ label
582 clocks = <&clks IMX5_CLK_I2C3_GATE>;
590 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
591 <&clks IMX5_CLK_UART4_PER_GATE>;
613 clocks = <&clks IMX5_CLK_IIM_GATE>;
620 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
621 <&clks IMX5_CLK_UART5_PER_GATE>;
629 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
639 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
640 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
649 clocks = <&clks IMX5_CLK_SDMA_GATE>,
650 <&clks IMX5_CLK_SDMA_GATE>;
662 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
663 <&clks IMX5_CLK_CSPI_IPG_GATE>;
674 clocks = <&clks IMX5_CLK_I2C2_GATE>;
684 clocks = <&clks IMX5_CLK_I2C1_GATE>;
694 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
695 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
714 clocks = <&clks IMX5_CLK_NFC_GATE>;
724 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
725 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
738 clocks = <&clks IMX5_CLK_FEC_GATE>,
739 <&clks IMX5_CLK_FEC_GATE>,
740 <&clks IMX5_CLK_FEC_GATE>;
749 clocks = <&clks IMX5_CLK_TVE_GATE>,
750 <&clks IMX5_CLK_IPU_DI1_SEL>;
765 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
766 <&clks IMX5_CLK_VPU_GATE>;
776 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
777 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
785 clocks = <&clks IMX5_CLK_OCRAM>;