Lines Matching refs:clocks

55 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
154 		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
164 		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
174 		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
184 		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
194 		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
208 		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
222 		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
236 		clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
289 		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
298 		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
307 		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
316 		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
325 		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
334 		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
343 		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
351 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
359 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
367 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
375 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
385 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
395 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
401 	clocks {
414 		/* Special CPG clocks */
416 			compatible = "renesas,r8a7778-cpg-clocks";
419 			clocks = <&extal_clk>;
424 		/* Audio clocks; frequencies are set by boards if applicable. */
441 		/* Fixed ratio clocks */
444 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
452 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
460 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
468 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
476 			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
483 		/* Gate clocks */
485 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
487 			clocks = <&cpg_clocks R8A7778_CLK_P>,
526 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
528 			clocks = <&cpg_clocks R8A7778_CLK_P>,
541 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
543 			clocks = <&s4_clk>,
565 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
567 			clocks = <&cpg_clocks R8A7778_CLK_P>,