Lines Matching refs:clocks
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
326 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
354 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
367 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
377 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
387 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
397 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
407 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
418 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
429 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
441 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
453 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
469 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
480 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
490 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
500 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
510 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
519 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
528 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
537 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
546 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
555 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
564 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
573 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
582 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
591 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
600 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
609 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
618 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
627 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
636 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
645 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
654 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
663 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
672 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
683 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
691 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
699 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
711 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
727 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
735 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
743 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
753 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
766 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
779 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
795 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
822 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
832 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
838 clocks {
853 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
854 * default. Boards that provide audio clocks should override them.
902 /* Special CPG clocks */
904 compatible = "renesas,r8a7791-cpg-clocks",
905 "renesas,rcar-gen2-cpg-clocks";
907 clocks = <&extal_clk &usb_extal_clk>;
914 /* Variable factor clocks */
918 clocks = <&pll1_div2_clk>;
925 clocks = <&pll1_div2_clk>;
932 clocks = <&pll1_div2_clk>;
939 clocks = <&pll1_div2_clk>;
946 clocks = <&pll1_div2_clk>;
951 /* Fixed factor clocks */
954 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
962 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
970 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
978 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
986 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
994 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1002 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1010 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1018 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1026 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1034 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1042 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1050 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1058 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1066 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1074 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1082 clocks = <&pll1_div2_clk>;
1090 clocks = <&extal_clk>;
1097 /* Gate clocks */
1099 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1101 clocks = <&mp_clk>;
1107 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1128 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1130 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1146 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1148 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1164 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1166 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1178 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1180 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1196 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1198 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1211 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1213 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1232 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1234 clocks = <&p_clk>,
1265 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1267 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1280 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1293 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1305 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1317 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1329 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1338 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1372 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1423 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1503 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,