Lines Matching refs:clock
13 #include <dt-bindings/clock/sh73a0-clock.h>
29 clock-frequency = <1196000000>;
36 clock-frequency = <1196000000>;
85 clock-names = "fck";
304 clock-names = "sci_ick";
314 clock-names = "sci_ick";
324 clock-names = "sci_ick";
334 clock-names = "sci_ick";
344 clock-names = "sci_ick";
354 clock-names = "sci_ick";
364 clock-names = "sci_ick";
374 clock-names = "sci_ick";
384 clock-names = "sci_ick";
545 compatible = "fixed-clock";
546 #clock-cells = <0>;
547 clock-frequency = <32768>;
548 clock-output-names = "extalr";
551 compatible = "fixed-clock";
552 #clock-cells = <0>;
553 clock-frequency = <26000000>;
554 clock-output-names = "extal1";
557 compatible = "fixed-clock";
558 #clock-cells = <0>;
559 clock-output-names = "extal2";
562 compatible = "fixed-clock";
563 #clock-cells = <0>;
564 clock-output-names = "extcki";
567 compatible = "fixed-clock";
568 #clock-cells = <0>;
569 clock-frequency = <0>;
570 clock-output-names = "fsiack";
573 compatible = "fixed-clock";
574 #clock-cells = <0>;
575 clock-frequency = <0>;
576 clock-output-names = "fsibck";
584 #clock-cells = <1>;
585 clock-output-names = "main", "pll0", "pll1", "pll2",
593 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
599 #clock-cells = <0>;
600 clock-output-names = "vclk1";
603 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
609 #clock-cells = <0>;
610 clock-output-names = "vclk2";
613 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
619 #clock-cells = <0>;
620 clock-output-names = "vclk3";
623 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
627 #clock-cells = <0>;
628 clock-output-names = "zb";
631 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
635 #clock-cells = <0>;
636 clock-output-names = "flctlck";
639 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
643 #clock-cells = <0>;
644 clock-output-names = "sdhi0ck";
647 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
651 #clock-cells = <0>;
652 clock-output-names = "sdhi1ck";
655 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
659 #clock-cells = <0>;
660 clock-output-names = "sdhi2ck";
663 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
667 #clock-cells = <0>;
668 clock-output-names = "fsia";
671 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
675 #clock-cells = <0>;
676 clock-output-names = "fsib";
679 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
683 #clock-cells = <0>;
684 clock-output-names = "sub";
687 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
691 #clock-cells = <0>;
692 clock-output-names = "spua";
695 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
699 #clock-cells = <0>;
700 clock-output-names = "spuv";
703 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
707 #clock-cells = <0>;
708 clock-output-names = "msu";
711 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
715 #clock-cells = <0>;
716 clock-output-names = "hsi";
719 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 #clock-cells = <0>;
724 clock-output-names = "mfg1";
727 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
731 #clock-cells = <0>;
732 clock-output-names = "mfg2";
735 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
739 #clock-cells = <0>;
740 clock-output-names = "dsit";
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
748 #clock-cells = <0>;
749 clock-output-names = "dsi0pck";
754 compatible = "fixed-factor-clock";
756 #clock-cells = <0>;
757 clock-div = <2>;
758 clock-mult = <1>;
759 clock-output-names = "main_div2";
762 compatible = "fixed-factor-clock";
764 #clock-cells = <0>;
765 clock-div = <2>;
766 clock-mult = <1>;
767 clock-output-names = "pll1_div2";
770 compatible = "fixed-factor-clock";
772 #clock-cells = <0>;
773 clock-div = <7>;
774 clock-mult = <1>;
775 clock-output-names = "pll1_div7";
778 compatible = "fixed-factor-clock";
780 #clock-cells = <0>;
781 clock-div = <13>;
782 clock-mult = <1>;
783 clock-output-names = "pll1_div13";
786 compatible = "fixed-factor-clock";
788 #clock-cells = <0>;
789 clock-div = <4>;
790 clock-mult = <1>;
791 clock-output-names = "twd";
799 #clock-cells = <1>;
800 clock-indices = <
803 clock-output-names =
817 #clock-cells = <1>;
818 clock-indices = <
825 clock-output-names =
836 #clock-cells = <1>;
837 clock-indices = <
844 clock-output-names =
861 #clock-cells = <1>;
862 clock-indices = <
872 clock-output-names =
882 #clock-cells = <1>;
883 clock-indices = <
887 clock-output-names =
894 #clock-cells = <1>;
895 clock-indices = <
898 clock-output-names =