Lines Matching refs:clocks
45 clocks = <&twd_clk>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
534 clocks = <&zb_clk>;
538 clocks {
543 /* External root clocks */
579 /* Special CPG clocks */
581 compatible = "renesas,sh73a0-cpg-clocks";
583 clocks = <&extal1_clk>, <&extal2_clk>;
591 /* Variable factor clocks (DIV6) */
595 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
605 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
615 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
625 clocks = <&pll1_div2_clk>, <0>,
633 clocks = <&pll1_div2_clk>, <0>,
641 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
649 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
657 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
665 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
673 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
681 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
689 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
697 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
705 clocks = <&pll1_div2_clk>, <0>,
713 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
721 clocks = <&pll1_div2_clk>, <0>,
729 clocks = <&pll1_div2_clk>, <0>,
737 clocks = <&pll1_div2_clk>, <0>,
745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
752 /* Fixed factor clocks */
755 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
763 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
771 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
779 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
787 clocks = <&cpg_clocks SH73A0_CLK_Z>;
794 /* Gate clocks */
796 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
798 clocks = <&cpg_clocks SH73A0_CLK_HP>;
807 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
809 clocks = <&cpg_clocks SH73A0_CLK_B>,
830 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
832 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
852 clocks = <&sub_clk>, <&extalr_clk>,
878 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
880 clocks = <&cpg_clocks SH73A0_CLK_HP>,
891 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
893 clocks = <&cpg_clocks SH73A0_CLK_HP>;