Lines Matching refs:clock
105 clock-names = "wdogclk", "apb_pclk";
113 clock-names = "pxlclk";
120 clock-names = "apb_pclk";
161 clock-names = "apb_pclk";
173 clock-names = "apb_pclk";
198 /* Reference 24MHz clock */
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <24000000>;
202 clock-output-names = "oscclk6a";
210 /* A15 PLL 0 reference clock */
214 #clock-cells = <0>;
215 clock-output-names = "oscclk0";
219 /* A15 PLL 1 reference clock */
223 #clock-cells = <0>;
224 clock-output-names = "oscclk1";
228 /* A7 PLL 0 reference clock */
232 #clock-cells = <0>;
233 clock-output-names = "oscclk2";
237 /* A7 PLL 1 reference clock */
241 #clock-cells = <0>;
242 clock-output-names = "oscclk3";
246 /* External AXI master clock */
250 #clock-cells = <0>;
251 clock-output-names = "oscclk4";
255 /* HDLCD PLL reference clock */
259 #clock-cells = <0>;
260 clock-output-names = "oscclk5";
264 /* Static memory controller clock */
268 #clock-cells = <0>;
269 clock-output-names = "oscclk6";
273 /* SYS PLL reference clock */
277 #clock-cells = <0>;
278 clock-output-names = "oscclk7";
282 /* DDR2 PLL reference clock */
286 #clock-cells = <0>;
287 clock-output-names = "oscclk8";
367 clock-names = "apb_pclk";
381 clock-names = "apb_pclk";
431 clock-names = "apb_pclk";
496 clock-names = "apb_pclk";
510 clock-names = "apb_pclk";
524 clock-names = "apb_pclk";
538 clock-names = "apb_pclk";
552 clock-names = "apb_pclk";