Lines Matching refs:str

226 	str	r2, [vcpu, #VCPU_USR_SP]
227 	str	r3, [vcpu, #VCPU_USR_LR]
232 	str	r2, [vcpu, #VCPU_PC]
233 	str	r3, [vcpu, #VCPU_CPSR]
264 	str	r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
265 	str	r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
266 	str	r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
267 	str	r5, [vcpu, #CP15_OFFSET(c3_DACR)]
272 	str	r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
273 	str	r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
274 	str	r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
292 	str	r2, [vcpu, #CP15_OFFSET(c13_CID)]
293 	str	r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
294 	str	r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
295 	str	r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
296 	str	r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
297 	str	r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
298 	str	r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
299 	str	r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
300 	str	r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
301 	str	r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
302 	str	r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
313 	str	r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
316 	str	r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
317 	str	r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
432 	str	r3, [r11, #VGIC_V2_CPU_HCR]
433 	str	r4, [r11, #VGIC_V2_CPU_VMCR]
434 	str	r5, [r11, #VGIC_V2_CPU_MISR]
436 	str	r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
437 	str	r7, [r11, #VGIC_V2_CPU_EISR]
438 	str	r8, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
439 	str	r9, [r11, #VGIC_V2_CPU_ELRSR]
441 	str	r6, [r11, #VGIC_V2_CPU_EISR]
442 	str	r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
443 	str	r8, [r11, #VGIC_V2_CPU_ELRSR]
444 	str	r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
446 	str	r10, [r11, #VGIC_V2_CPU_APR]
450 	str	r5, [r2, #GICH_HCR]
458 	str	r6, [r3], #4
487 	str	r3, [r2, #GICH_HCR]
488 	str	r4, [r2, #GICH_VMCR]
489 	str	r8, [r2, #GICH_APR]
497 	str	r6, [r2], #4
520 	str	r2, [vcpu, #VCPU_TIMER_CNTV_CTL]