126 	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);  in irq_resume()
127 	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);  in irq_resume()
129 	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);  in irq_resume()
157 	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,  in ap_flash_init()
162 	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);  in ap_flash_init()
166 		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);  in ap_flash_init()
167 		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);  in ap_flash_init()
168 		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);  in ap_flash_init()
177 	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,  in ap_flash_exit()
182 	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);  in ap_flash_exit()
186 		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);  in ap_flash_exit()
187 		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);  in ap_flash_exit()
188 		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);  in ap_flash_exit()
195 		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,  in ap_flash_set_vpp()
198 		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,  in ap_flash_set_vpp()