17 static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;  variable
38 		reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */  in qmgr_set_irq()
58 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);  in qmgr_irq1_a0()
60 	en_bitmap = qmgr_regs->irqen[0];  in qmgr_irq1_a0()
64 		src = qmgr_regs->irqsrc[i >> 3];  in qmgr_irq1_a0()
65 		stat = qmgr_regs->stat1[i >> 3];  in qmgr_irq1_a0()
83 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);  in qmgr_irq2_a0()
85 	req_bitmap = qmgr_regs->irqen[1] & qmgr_regs->statne_h;  in qmgr_irq2_a0()
99 	u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);  in qmgr_irq()
103 	__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */  in qmgr_irq()
122 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,  in qmgr_enable_irq()
123 		     &qmgr_regs->irqen[half]);  in qmgr_enable_irq()
134 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,  in qmgr_disable_irq()
135 		     &qmgr_regs->irqen[half]);  in qmgr_disable_irq()
136 	__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */  in qmgr_disable_irq()
197 	if (__raw_readl(&qmgr_regs->sram[queue])) {  in qmgr_request_queue()
211 		if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {  in qmgr_request_queue()
223 	__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);  in qmgr_request_queue()
246 	cfg = __raw_readl(&qmgr_regs->sram[queue]);  in qmgr_release_queue()
273 	__raw_writel(0, &qmgr_regs->sram[queue]);  in qmgr_release_queue()
298 		__raw_writel(0x33333333, &qmgr_regs->stat1[i]);  in qmgr_init()
299 		__raw_writel(0, &qmgr_regs->irqsrc[i]);  in qmgr_init()
302 		__raw_writel(0, &qmgr_regs->stat2[i]);  in qmgr_init()
303 		__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */  in qmgr_init()
304 		__raw_writel(0, &qmgr_regs->irqen[i]);  in qmgr_init()
307 	__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);  in qmgr_init()
308 	__raw_writel(0, &qmgr_regs->statf_h);  in qmgr_init()
311 		__raw_writel(0, &qmgr_regs->sram[i]);  in qmgr_init()