69 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)  in wakeupgen_writel()  argument
71 	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +  in wakeupgen_writel()
75 static inline void sar_writel(u32 val, u32 offset, u8 idx)  in sar_writel()  argument
77 	writel_relaxed(val, sar_base + offset + (idx * 4));  in sar_writel()
94 	u32 val, bit_number;  in _wakeupgen_clear()  local
100 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_clear()
101 	val &= ~BIT(bit_number);  in _wakeupgen_clear()
102 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_clear()
107 	u32 val, bit_number;  in _wakeupgen_set()  local
113 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_set()
114 	val |= BIT(bit_number);  in _wakeupgen_set()
115 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_set()
197 	u32 i, val;  in omap4_irq_save_context()  local
204 		val = wakeupgen_readl(i, 0);  in omap4_irq_save_context()
205 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);  in omap4_irq_save_context()
206 		val = wakeupgen_readl(i, 1);  in omap4_irq_save_context()
207 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);  in omap4_irq_save_context()
221 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap4_irq_save_context()
222 	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);  in omap4_irq_save_context()
223 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);  in omap4_irq_save_context()
224 	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);  in omap4_irq_save_context()
227 	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);  in omap4_irq_save_context()
228 	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);  in omap4_irq_save_context()
229 	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);  in omap4_irq_save_context()
230 	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);  in omap4_irq_save_context()
233 	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);  in omap4_irq_save_context()
234 	val |= SAR_BACKUP_STATUS_WAKEUPGEN;  in omap4_irq_save_context()
235 	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);  in omap4_irq_save_context()
241 	u32 i, val;  in omap5_irq_save_context()  local
245 		val = wakeupgen_readl(i, 0);  in omap5_irq_save_context()
246 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);  in omap5_irq_save_context()
247 		val = wakeupgen_readl(i, 1);  in omap5_irq_save_context()
248 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);  in omap5_irq_save_context()
254 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap5_irq_save_context()
255 	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);  in omap5_irq_save_context()
256 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap5_irq_save_context()
257 	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);  in omap5_irq_save_context()
260 	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);  in omap5_irq_save_context()
261 	val |= SAR_BACKUP_STATUS_WAKEUPGEN;  in omap5_irq_save_context()
262 	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);  in omap5_irq_save_context()
290 	u32 val;  in irq_sar_clear()  local
296 	val = readl_relaxed(sar_base + offset);  in irq_sar_clear()
297 	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;  in irq_sar_clear()
298 	writel_relaxed(val, sar_base + offset);  in irq_sar_clear()
463 	u32 val;  in wakeupgen_init()  local
530 		val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);  in wakeupgen_init()
531 		val |= BIT(5);  in wakeupgen_init()
532 		omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);  in wakeupgen_init()