Lines Matching refs:SH_CLK_DIV6_EXT
397 [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
399 [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
401 [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
403 [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
405 [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
407 [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
409 [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
411 [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
413 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
415 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
417 [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
419 [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
421 [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
423 [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
425 [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
427 [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
429 [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
431 [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
433 [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
435 [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,