Lines Matching refs:str
108 str r2, [r3, r1] @ put flow controller in wait event mode
115 str r1, [r3, #0x340] @ put slave CPU in reset
158 str r12, [r2] @ flag[cpu] = 1
160 str r12, [r1] @ !turn = cpu
179 str r12, [r2]
348 str r1, [r0, #CLK_RESET_SCLK_BURST]
349 str r1, [r0, #CLK_RESET_CCLK_BURST]
351 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
352 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
367 str r1, [r7] @ restore the value in pad_save
382 str r4, [r0, #CLK_RESET_SCLK_BURST]
384 str r4, [r0, #CLK_RESET_CCLK_BURST]
389 str r1, [r0, #EMC_CFG]
392 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
394 str r1, [r0, #EMC_NOP]
395 str r1, [r0, #EMC_NOP]
396 str r1, [r0, #EMC_REFRESH]
406 str r1, [r0, #EMC_REQ_CTRL]
436 str r0, [r5, #CLK_RESET_SCLK_BURST]
437 str r0, [r5, #CLK_RESET_CCLK_BURST]
439 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
440 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
451 str r0, [r5, #CLK_RESET_PLLM_BASE]
454 str r0, [r5, #CLK_RESET_PLLP_BASE]
457 str r0, [r5, #CLK_RESET_PLLC_BASE]
461 str r0, [r5, #CLK_RESET_SCLK_BURST]
479 str r0, [r6, r1]
500 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
508 str r2, [r1, #EMC_SELF_REF]
528 str r1, [r4, r5] @ save the content of the addr
531 str r1, [r0] @ set the save val to the addr
541 str r0, [r2]