Lines Matching refs:mcr

94 1:	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
96 	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
98 	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
100 	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
120 	mcr	p15, 0, r1, c1, c0, 1
130 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
149 	mcr	p15, 0, r1, c10, c4, 1		@ unlock I-TLB
150 	mcr	p15, 0, r1, c8, c5, 0		@ invalidate I-TLB
156 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
158 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches & BTB
159 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
162 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
181 	mcr	p14, 0, r0, c7, c0, 0		@ Go to IDLE
193 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
240 	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
241 	mcr	p15, 0, r0, c7, c6, 1		@ Invalidate D cache line
265 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
270 	mcr	p15, 0, r0, c7, c5, 0		@ Invalidate I cache & BTB
271 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
286 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
287 	mcr	p15, 0, r0, c7, c5, 1		@ Invalidate I cache entry
292 	mcr	p15, 0, r0, c7, c5, 6		@ Invalidate BTB
293 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
307 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
308 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
313 	mcr	p15, 0, r0, c7, c5, 0		@ Invalidate I cache & BTB
314 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
334 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
338 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
351 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
355 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
368 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
369 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
373 	mcr	p15, 0, r0, c7, c10, 4		@ Drain Write (& Fill) Buffer
457 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
475 	mcr	p15, 0, ip, c7, c5, 0		@ Invalidate I cache & BTB
476 	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
477 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
478 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
548 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I & D TLBs
549 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB
550 	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
551 	mcr	p15, 0, r5, c15, c1, 0	@ CP access reg
552 	mcr	p15, 0, r6, c13, c0, 0	@ PID
553 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
554 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
555 	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
563 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I, D caches & BTB
564 	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
565 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I, D TLBs
568 	mcr	p15, 0, r0, c15, c1, 0		@ affects USR or SVC modes