Lines Matching refs:aarch64_insn_register

85 enum aarch64_insn_register {  enum
294 				     enum aarch64_insn_register reg,
301 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
303 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
304 				    enum aarch64_insn_register base,
305 				    enum aarch64_insn_register offset,
308 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
309 				     enum aarch64_insn_register reg2,
310 				     enum aarch64_insn_register base,
314 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
315 				 enum aarch64_insn_register src,
318 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
319 			      enum aarch64_insn_register src,
323 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
327 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
328 					 enum aarch64_insn_register src,
329 					 enum aarch64_insn_register reg,
333 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
334 			   enum aarch64_insn_register src,
337 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
338 			   enum aarch64_insn_register src,
339 			   enum aarch64_insn_register reg,
342 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
343 			   enum aarch64_insn_register src,
344 			   enum aarch64_insn_register reg1,
345 			   enum aarch64_insn_register reg2,
348 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
349 					 enum aarch64_insn_register src,
350 					 enum aarch64_insn_register reg,