Lines Matching refs:UL
26 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
36 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
46 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
54 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
140 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
147 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
148 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
151 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
152 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
153 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
154 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
155 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
156 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
157 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
158 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
159 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
160 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
161 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
162 #define TCR_TG0_4K (UL(0) << 14)
163 #define TCR_TG0_64K (UL(1) << 14)
164 #define TCR_TG0_16K (UL(2) << 14)
165 #define TCR_TG1_16K (UL(1) << 30)
166 #define TCR_TG1_4K (UL(2) << 30)
167 #define TCR_TG1_64K (UL(3) << 30)
168 #define TCR_ASID16 (UL(1) << 36)
169 #define TCR_TBI0 (UL(1) << 37)