233 	int i, max_slots, ctrl_reg, val_reg, reg_enable;  in hw_breakpoint_control()  local
239 		ctrl_reg = AARCH64_DBG_REG_BCR;  in hw_breakpoint_control()
246 		ctrl_reg = AARCH64_DBG_REG_WCR;  in hw_breakpoint_control()
272 		write_wb_reg(ctrl_reg, i,  in hw_breakpoint_control()
277 		write_wb_reg(ctrl_reg, i, 0);  in hw_breakpoint_control()
584 	u32 ctrl_reg;  in breakpoint_handler()  local
608 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);  in breakpoint_handler()
609 		decode_ctrl_reg(ctrl_reg, &ctrl);  in breakpoint_handler()
660 	u32 ctrl_reg;  in watchpoint_handler()  local
695 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);  in watchpoint_handler()
696 		decode_ctrl_reg(ctrl_reg, &ctrl);  in watchpoint_handler()