272 	int shift;  in aarch64_get_imm_shift_mask()  local
277 		shift = 0;  in aarch64_get_imm_shift_mask()
281 		shift = 5;  in aarch64_get_imm_shift_mask()
285 		shift = 5;  in aarch64_get_imm_shift_mask()
289 		shift = 5;  in aarch64_get_imm_shift_mask()
293 		shift = 10;  in aarch64_get_imm_shift_mask()
297 		shift = 12;  in aarch64_get_imm_shift_mask()
301 		shift = 15;  in aarch64_get_imm_shift_mask()
306 		shift = 10;  in aarch64_get_imm_shift_mask()
310 		shift = 16;  in aarch64_get_imm_shift_mask()
317 	*shiftp = shift;  in aarch64_get_imm_shift_mask()
332 	int shift;  in aarch64_insn_decode_immediate()  local
336 		shift = 0;  in aarch64_insn_decode_immediate()
343 		if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {  in aarch64_insn_decode_immediate()
350 	return (insn >> shift) & mask;  in aarch64_insn_decode_immediate()
357 	int shift;  in aarch64_insn_encode_immediate()  local
361 		shift = 0;  in aarch64_insn_encode_immediate()
370 		if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {  in aarch64_insn_encode_immediate()
378 	insn &= ~(mask << shift);  in aarch64_insn_encode_immediate()
379 	insn |= (imm & mask) << shift;  in aarch64_insn_encode_immediate()
388 	int shift;  in aarch64_insn_encode_register()  local
398 		shift = 0;  in aarch64_insn_encode_register()
401 		shift = 5;  in aarch64_insn_encode_register()
405 		shift = 10;  in aarch64_insn_encode_register()
408 		shift = 16;  in aarch64_insn_encode_register()
416 	insn &= ~(GENMASK(4, 0) << shift);  in aarch64_insn_encode_register()
417 	insn |= reg << shift;  in aarch64_insn_encode_register()
625 	int shift;  in aarch64_insn_gen_load_store_pair()  local
650 		shift = 2;  in aarch64_insn_gen_load_store_pair()
656 		shift = 3;  in aarch64_insn_gen_load_store_pair()
674 					     offset >> shift);  in aarch64_insn_gen_load_store_pair()
772 			      int imm, int shift,  in aarch64_insn_gen_movewide()  argument
797 		BUG_ON(shift != 0 && shift != 16);  in aarch64_insn_gen_movewide()
801 		BUG_ON(shift != 0 && shift != 16 && shift != 32 &&  in aarch64_insn_gen_movewide()
802 		       shift != 48);  in aarch64_insn_gen_movewide()
809 	insn |= (shift >> 4) << 21;  in aarch64_insn_gen_movewide()
819 					 int shift,  in aarch64_insn_gen_add_sub_shifted_reg()  argument
845 		BUG_ON(shift & ~(SZ_32 - 1));  in aarch64_insn_gen_add_sub_shifted_reg()
849 		BUG_ON(shift & ~(SZ_64 - 1));  in aarch64_insn_gen_add_sub_shifted_reg()
863 	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);  in aarch64_insn_gen_add_sub_shifted_reg()
1001 					 int shift,  in aarch64_insn_gen_logical_shifted_reg()  argument
1039 		BUG_ON(shift & ~(SZ_32 - 1));  in aarch64_insn_gen_logical_shifted_reg()
1043 		BUG_ON(shift & ~(SZ_64 - 1));  in aarch64_insn_gen_logical_shifted_reg()
1057 	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);  in aarch64_insn_gen_logical_shifted_reg()