153 			int idx)  in armpmu_event_set_period()  argument
185 	armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);  in armpmu_event_set_period()
195 		    int idx)  in armpmu_event_update()  argument
202 	new_raw_count = armpmu->read_counter(idx);  in armpmu_event_update()
222 	if (hwc->idx < 0)  in armpmu_read()
225 	armpmu_event_update(event, hwc, hwc->idx);  in armpmu_read()
239 		armpmu->disable(hwc, hwc->idx);  in armpmu_stop()
241 		armpmu_event_update(event, hwc, hwc->idx);  in armpmu_stop()
267 	armpmu_event_set_period(event, hwc, hwc->idx);  in armpmu_start()
268 	armpmu->enable(hwc, hwc->idx);  in armpmu_start()
277 	int idx = hwc->idx;  in armpmu_del()  local
279 	WARN_ON(idx < 0);  in armpmu_del()
282 	hw_events->events[idx] = NULL;  in armpmu_del()
283 	clear_bit(idx, hw_events->used_mask);  in armpmu_del()
294 	int idx;  in armpmu_add()  local
300 	idx = armpmu->get_event_idx(hw_events, hwc);  in armpmu_add()
301 	if (idx < 0) {  in armpmu_add()
302 		err = idx;  in armpmu_add()
310 	event->hw.idx = idx;  in armpmu_add()
311 	armpmu->disable(hwc, idx);  in armpmu_add()
312 	hw_events->events[idx] = event;  in armpmu_add()
548 	hwc->idx		= -1;  in __hw_perf_event_init()
891 static inline int armv8pmu_counter_valid(int idx)  in armv8pmu_counter_valid()  argument
893 	return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;  in armv8pmu_counter_valid()
896 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)  in armv8pmu_counter_has_overflowed()  argument
901 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_counter_has_overflowed()
903 			smp_processor_id(), idx);  in armv8pmu_counter_has_overflowed()
905 		counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_counter_has_overflowed()
912 static inline int armv8pmu_select_counter(int idx)  in armv8pmu_select_counter()  argument
916 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_select_counter()
918 			smp_processor_id(), idx);  in armv8pmu_select_counter()
922 	counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_select_counter()
926 	return idx;  in armv8pmu_select_counter()
929 static inline u32 armv8pmu_read_counter(int idx)  in armv8pmu_read_counter()  argument
933 	if (!armv8pmu_counter_valid(idx))  in armv8pmu_read_counter()
935 			smp_processor_id(), idx);  in armv8pmu_read_counter()
936 	else if (idx == ARMV8_IDX_CYCLE_COUNTER)  in armv8pmu_read_counter()
938 	else if (armv8pmu_select_counter(idx) == idx)  in armv8pmu_read_counter()
944 static inline void armv8pmu_write_counter(int idx, u32 value)  in armv8pmu_write_counter()  argument
946 	if (!armv8pmu_counter_valid(idx))  in armv8pmu_write_counter()
948 			smp_processor_id(), idx);  in armv8pmu_write_counter()
949 	else if (idx == ARMV8_IDX_CYCLE_COUNTER)  in armv8pmu_write_counter()
951 	else if (armv8pmu_select_counter(idx) == idx)  in armv8pmu_write_counter()
955 static inline void armv8pmu_write_evtype(int idx, u32 val)  in armv8pmu_write_evtype()  argument
957 	if (armv8pmu_select_counter(idx) == idx) {  in armv8pmu_write_evtype()
963 static inline int armv8pmu_enable_counter(int idx)  in armv8pmu_enable_counter()  argument
967 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_enable_counter()
969 			smp_processor_id(), idx);  in armv8pmu_enable_counter()
973 	counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_enable_counter()
975 	return idx;  in armv8pmu_enable_counter()
978 static inline int armv8pmu_disable_counter(int idx)  in armv8pmu_disable_counter()  argument
982 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_disable_counter()
984 			smp_processor_id(), idx);  in armv8pmu_disable_counter()
988 	counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_disable_counter()
990 	return idx;  in armv8pmu_disable_counter()
993 static inline int armv8pmu_enable_intens(int idx)  in armv8pmu_enable_intens()  argument
997 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_enable_intens()
999 			smp_processor_id(), idx);  in armv8pmu_enable_intens()
1003 	counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_enable_intens()
1005 	return idx;  in armv8pmu_enable_intens()
1008 static inline int armv8pmu_disable_intens(int idx)  in armv8pmu_disable_intens()  argument
1012 	if (!armv8pmu_counter_valid(idx)) {  in armv8pmu_disable_intens()
1014 			smp_processor_id(), idx);  in armv8pmu_disable_intens()
1018 	counter = ARMV8_IDX_TO_COUNTER(idx);  in armv8pmu_disable_intens()
1024 	return idx;  in armv8pmu_disable_intens()
1041 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)  in armv8pmu_enable_event()  argument
1055 	armv8pmu_disable_counter(idx);  in armv8pmu_enable_event()
1060 	armv8pmu_write_evtype(idx, hwc->config_base);  in armv8pmu_enable_event()
1065 	armv8pmu_enable_intens(idx);  in armv8pmu_enable_event()
1070 	armv8pmu_enable_counter(idx);  in armv8pmu_enable_event()
1075 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)  in armv8pmu_disable_event()  argument
1088 	armv8pmu_disable_counter(idx);  in armv8pmu_disable_event()
1093 	armv8pmu_disable_intens(idx);  in armv8pmu_disable_event()
1104 	int idx;  in armv8pmu_handle_irq()  local
1123 	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {  in armv8pmu_handle_irq()
1124 		struct perf_event *event = cpuc->events[idx];  in armv8pmu_handle_irq()
1135 		if (!armv8pmu_counter_has_overflowed(pmovsr, idx))  in armv8pmu_handle_irq()
1139 		armpmu_event_update(event, hwc, idx);  in armv8pmu_handle_irq()
1141 		if (!armpmu_event_set_period(event, hwc, idx))  in armv8pmu_handle_irq()
1145 			cpu_pmu->disable(hwc, idx);  in armv8pmu_handle_irq()
1185 	int idx;  in armv8pmu_get_event_idx()  local
1200 	for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {  in armv8pmu_get_event_idx()
1201 		if (!test_and_set_bit(idx, cpuc->used_mask))  in armv8pmu_get_event_idx()
1202 			return idx;  in armv8pmu_get_event_idx()
1237 	u32 idx, nb_cnt = cpu_pmu->num_events;  in armv8pmu_reset()  local
1240 	for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)  in armv8pmu_reset()
1241 		armv8pmu_disable_event(NULL, idx);  in armv8pmu_reset()