Lines Matching refs:add

44 	add	x3, x2, #CPU_XREG_OFFSET(19)
80 	add	x3, x2, #CPU_XREG_OFFSET(31)    // SP_EL0
88 	add	x3, x2, #CPU_XREG_OFFSET(19)
108 	add	x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
115 	add	x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
127 	add	x3, x2, #CPU_XREG_OFFSET(4)
140 	add	x3, x2, #CPU_XREG_OFFSET(0)
153 	add	x3, x2, #CPU_XREG_OFFSET(0)
193 	add	x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
242 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
245 	add	x26, x26, x24, lsl #2
266 	add	x26, x26, x24, lsl #2
287 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
290 	add	x26, x26, x24, lsl #2
311 	add	x26, x26, x24, lsl #2
332 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
335 	add	x26, x26, x25, lsl #2
356 	add	x26, x26, x25, lsl #2
377 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
380 	add	x26, x26, x25, lsl #2
401 	add	x26, x26, x25, lsl #2
430 	add	x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
479 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
482 	add	x26, x26, x24, lsl #2
503 	add	x26, x26, x24, lsl #2
523 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
526 	add	x26, x26, x24, lsl #2
547 	add	x26, x26, x24, lsl #2
567 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
570 	add	x26, x26, x25, lsl #2
591 	add	x26, x26, x25, lsl #2
611 	add	x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
614 	add	x26, x26, x25, lsl #2
635 	add	x26, x26, x25, lsl #2
679 	add	x25, x0, #VCPU_CONTEXT
703 	add	x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
711 	add	x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
724 	add	x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
734 	add	x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
742 	add	x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
755 	add	x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
949 	add	x2, x0, #VCPU_CONTEXT
970 	add	x2, x0, #VCPU_CONTEXT
1095 	add	x0, x0, x3