Lines Matching refs:x0
54 mrs x0, sctlr_el1
55 bic x0, x0, #1 << 2 // clear SCTLR.C
56 msr sctlr_el1, x0
76 ret x0
81 mov x19, x0
90 mov x0, x20
123 stp x2, x3, [x0]
124 stp x4, x5, [x0, #16]
125 stp x6, x7, [x0, #32]
126 stp x8, x9, [x0, #48]
127 stp x10, x11, [x0, #64]
128 str x12, [x0, #80]
146 ldp x2, x3, [x0]
147 ldp x4, x5, [x0, #16]
148 ldp x6, x7, [x0, #32]
149 ldp x8, x9, [x0, #48]
150 ldp x10, x11, [x0, #64]
151 ldr x12, [x0, #80]
168 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
169 mov x0, x12
185 bfi x0, x1, #48, #16 // set the ASID
186 msr ttbr0_el1, x0 // set TTBR0
204 mov x0, #3 << 20
205 msr cpacr_el1, x0 // Enable FP/ASIMD
206 mov x0, #1 << 12 // Reset mdscr_el1 and disable
207 msr mdscr_el1, x0 // access to the DCC from EL0
208 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
231 mrs x0, sctlr_el1
232 bic x0, x0, x5 // clear bits
233 orr x0, x0, x6 // set bits