Lines Matching refs:P0
19 P0.H = hi(PLL_CTL);
20 P0.L = lo(PLL_CTL);
21 R1 = W[P0](z);
23 W[P0] = R1.L;
38 P0.H = hi(PLL_CTL);
39 P0.L = lo(PLL_CTL);
106 P0.H = hi(PLL_DIV);
107 P0.L = lo(PLL_DIV);
108 R6 = W[P0](z);
110 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
112 P0.H = hi(PLL_CTL);
113 P0.L = lo(PLL_CTL);
114 R5 = W[P0](z);
116 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
123 P0.H = hi(VR_CTL);
124 P0.L = lo(VR_CTL);
125 R7 = W[P0](z);
132 W[P0] = R2; /* Set Min Core Voltage */
144 P0.H = hi(PLL_CTL);
145 P0.L = lo(PLL_CTL);
146 R0 = W[P0](z);
148 W[P0] = R0.L; /* Turn CCLK OFF */
160 P0.H = hi(VR_CTL);
161 P0.L = lo(VR_CTL);
162 W[P0]= R7;
171 P0.H = hi(PLL_DIV);
172 P0.L = lo(PLL_DIV);
173 W[P0]= R6; /* Restore CCLK and SCLK divider */
175 P0.H = hi(PLL_CTL);
176 P0.L = lo(PLL_CTL);
194 P0.H = hi(EBIU_RSTCTL);
195 P0.L = lo(EBIU_RSTCTL);
196 R2 = [P0];
198 [P0] = R2;
201 R2 = [P0];
205 P0.L = lo(EBIU_SDGCTL);
206 P0.H = hi(EBIU_SDGCTL);
210 R2 = [P0];
212 [P0] = R2;
221 R2 = [P0];
223 [P0] = R2;
232 P0.H = hi(EBIU_RSTCTL);
233 P0.L = lo(EBIU_RSTCTL);
234 R2 = [P0];
236 [P0] = R2;
239 P0.L = lo(EBIU_SDGCTL);
240 P0.H = hi(EBIU_SDGCTL);
242 R2 = [P0];
244 [P0] = R2
248 R2 = [P0];
250 [P0] = R2
259 P0.H = hi(SYSMMR_BASE);
260 P0.L = lo(SYSMMR_BASE);
261 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
262 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
264 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
267 P0.H = hi(SIC_IWR);
268 P0.L = lo(SIC_IWR);
269 [P0] = R0;
277 P0.H = hi(PLL_STAT);
278 P0.L = lo(PLL_STAT);
280 R0 = W[P0] (Z);
298 P0 = 0; define
303 [P0++] = R1; /* Store Hibernate Magic */
304 [P0++] = R2; /* Save Return Address */
305 [P0++] = SP; /* Save Stack Pointer */