Lines Matching refs:mov
42 mov dest=src;; \
47 mov reg=_tmp
50 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
51 mov _idx=0;; \
58 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
59 mov _idx=0;; \
66 mov _reg=rr[_tmp]
89 mov ar.lc=0x08-1;; \
94 mov rr[_idx2]=_tmp;; \
166 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
167 mov rr[_tmp1]=_tmp2
211 mov r25=pr;;
237 mov r18=KERNEL_TR_PAGE_SHIFT<<2
240 mov cr.itir=r18
241 mov cr.ifa=r17
242 mov r16=IA64_TR_KERNEL
243 mov r3=ip
264 mov cr.ipsr=r16
267 mov cr.iip=r17
268 mov cr.ifs=r0
283 mov cr.iva=r3
289 mov ar.fpsr=r2
307 (isAP) mov r2=r3
314 mov r16=-1
327 mov r17=rr[r2]
332 mov cr.itir=r17
333 mov cr.ifa=r2
335 mov r19=IA64_TR_CURRENT_STACK
345 mov IA64_KR(CURRENT)=r2 // virtual address
346 mov IA64_KR(CURRENT_STACK)=r16
347 mov r13=r2
358 mov ar.rsc=0 // place RSE in enforced lazy mode
362 mov r18=PERCPU_PAGE_SIZE
378 mov r19=r20
385 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
386 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
388 mov ar.bspstore=r2 // establish the new RSE stack
390 mov ar.rsc=0x3 // place RSE in eager mode
401 mov r16=num_hypervisor_hooks
410 (p7) mov b1=r9
461 mov r20=ar.lc // preserve ar.lc
462 mov ar.lc=IA64_NUM_DBG_REGS-1
463 mov r18=0
466 1: mov r16=dbr[r18]
471 mov r17=ibr[r18]
478 mov ar.lc=r20 // restore ar.lc
485 mov r20=ar.lc // preserve ar.lc
487 mov ar.lc=IA64_NUM_DBG_REGS-1
488 mov r18=-1
494 mov dbr[r18]=r16
499 mov ibr[r18]=r17
502 mov ar.lc=r20 // restore ar.lc
676 mov loc0=512
677 mov loc1=-1024+16
803 mov f32=f0 // F
808 mov f37=f0 // F
813 mov f40=f0 // F
817 mov f45=f0 // F
821 mov f48=f0 // F
825 mov f53=f0 // F
829 mov f56=f0 // F
833 mov f61=f0 // F
837 mov f64=f0 // F
841 mov f69=f0 // F
845 mov f72=f0 // F
849 mov f77=f0 // F
853 mov f80=f0 // F
857 mov f85=f0 // F
861 mov f88=f0 // F
873 mov f93=f0 // F
877 mov f96=f0 // F
881 mov f101=f0 // F
885 mov f104=f0 // F
889 mov f109=f0 // F
893 mov f112=f0 // F
897 mov f117=f0 // F
901 mov f120=f0 // F
905 mov f125=f0 // F
926 mov r15=ip
934 mov cr.ipsr=r16 // set new PSR
937 mov r19=ar.bsp
938 mov r20=sp
939 mov r14=rp // get return address into a general register
949 mov r18=ar.rnat // save ar.rnat
950 mov ar.bspstore=r17 // this steps on ar.rnat
951 mov cr.iip=r3
952 mov cr.ifs=r0
954 mov ar.rnat=r18 // restore ar.rnat
957 1: mov rp=r14
974 mov r15=ip
982 mov cr.ipsr=r16 // set new PSR
985 mov r14=rp // get return address into a general register
994 mov sp=r20
1000 mov r18=ar.rnat // save ar.rnat
1001 mov ar.bspstore=r19 // this steps on ar.rnat
1002 mov cr.iip=r3
1003 mov cr.ifs=r0
1005 mov ar.rnat=r18 // restore ar.rnat
1008 1: mov rp=r14
1016 mov r2=ar.lc
1019 mov ar.lc=r32
1027 mov ar.lc=r2
1051 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1102 mov reg=r32; \
1128 mov b1=r18 // Return location
1131 mov b2=r18 // doing tlb_flush work
1132 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1135 mov cr.iip=r17
1137 mov cr.ipsr=r16
1138 mov cr.ifs=r0;;
1176 mov pr=r17,-1;;