96 #define PMC_IS_LAST(i)	(pmu_conf->pmc_desc[i].type & PFM_REG_END)
97 #define PMD_IS_LAST(i)	(pmu_conf->pmd_desc[i].type & PFM_REG_END)
102 #define PMC_IS_IMPL(i)	  (i< PMU_MAX_PMCS && (pmu_conf->pmc_desc[i].type & PFM_REG_IMPL))
103 #define PMD_IS_IMPL(i)	  (i< PMU_MAX_PMDS && (pmu_conf->pmd_desc[i].type & PFM_REG_IMPL))
106 #define PMD_IS_COUNTING(i) ((pmu_conf->pmd_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING)
107 #define PMC_IS_COUNTING(i) ((pmu_conf->pmc_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING)
108 #define PMC_IS_MONITOR(i)  ((pmu_conf->pmc_desc[i].type & PFM_REG_MONITOR)  == PFM_REG_MONITOR)
109 #define PMC_IS_CONTROL(i)  ((pmu_conf->pmc_desc[i].type & PFM_REG_CONTROL)  == PFM_REG_CONTROL)
111 #define PMC_DFL_VAL(i)     pmu_conf->pmc_desc[i].default_value
112 #define PMC_RSVD_MASK(i)   pmu_conf->pmc_desc[i].reserved_mask
113 #define PMD_PMD_DEP(i)	   pmu_conf->pmd_desc[i].dep_pmd[0]
114 #define PMC_PMD_DEP(i)	   pmu_conf->pmc_desc[i].dep_pmd[0]
401 #define PMC_PM(cnum, val)	(((val) >> (pmu_conf->pmc_desc[cnum].pm_pos)) & 0x1)
518 static pmu_config_t		*pmu_conf;  variable
749 	return ctx->ctx_pmds[i].val + (ia64_get_pmd(i) & pmu_conf->ovfl_val);  in pfm_read_soft_counter()
758 	unsigned long ovfl_val = pmu_conf->ovfl_val;  in pfm_write_soft_counter()
929 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_mask_monitoring()
1003 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_restore_monitoring()
1075 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_restore_monitoring()
1076 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_restore_monitoring()
1109 	unsigned long val, ovfl_val = pmu_conf->ovfl_val;  in pfm_restore_pmds()
1125 	unsigned long ovfl_val = pmu_conf->ovfl_val;  in pfm_copy_pmds()
2510 	ctx->ctx_all_pmcs[0] = pmu_conf->impl_pmcs[0] & ~0x1;  in pfm_reset_pmu_state()
2515 	ctx->ctx_all_pmds[0] = pmu_conf->impl_pmds[0];  in pfm_reset_pmu_state()
2838 	impl_pmds = pmu_conf->impl_pmds[0];  in pfm_write_pmcs()
2871 		pmc_type   = pmu_conf->pmc_desc[cnum].type;  in pfm_write_pmcs()
2872 		pmc_pm     = (value >> pmu_conf->pmc_desc[cnum].pm_pos) & 0x1;  in pfm_write_pmcs()
2885 		wr_func = pmu_conf->pmc_desc[cnum].write_check;  in pfm_write_pmcs()
2986 		CTX_USED_PMD(ctx, pmu_conf->pmc_desc[cnum].dep_pmd[0]);  in pfm_write_pmcs()
3076 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_write_pmds()
3109 		wr_func     = pmu_conf->pmd_desc[cnum].write_check;  in pfm_write_pmds()
3276 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_read_pmds()
3345 		rd_func = pmu_conf->pmd_desc[cnum].read_check;  in pfm_read_pmds()
3440 	if (pmu_conf->use_rr_dbregs == 0) return 0;  in pfm_use_debug_registers()
3494 	if (pmu_conf->use_rr_dbregs == 0) return 0;  in pfm_release_debug_registers()
3695 	if (pmu_conf->use_rr_dbregs == 0) return -EINVAL;  in pfm_write_ibr_dbr()
3777 		for (i=0; i < pmu_conf->num_ibrs; i++) {  in pfm_write_ibr_dbr()
3782 		for (i=0; i < pmu_conf->num_dbrs; i++) {  in pfm_write_ibr_dbr()
4352 			pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_context_load()
4353 			pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_context_load()
4778 	if (unlikely(pmu_conf == NULL)) return -ENOSYS;  in sys_perfmonctl()
5196 	ovfl_val = pmu_conf->ovfl_val;  in pfm_overflow_handler()
5610 		pmu_conf->pmu_name,  in pfm_proc_show_header()
5613 		pmu_conf->ovfl_val,  in pfm_proc_show_header()
5614 		pmu_conf->flags);  in pfm_proc_show_header()
6016 	need_irq_resend = pmu_conf->flags & PFM_PMU_IRQ_RESEND;  in pfm_load_regs()
6043 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_load_regs()
6044 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_load_regs()
6177 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_load_regs()
6178 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_load_regs()
6185 	need_irq_resend = pmu_conf->flags & PFM_PMU_IRQ_RESEND;  in pfm_load_regs()
6321 	ovfl_val = pmu_conf->ovfl_val;  in pfm_flush_pmds()
6542 	pmu_conf = *p;  in pfm_probe_pmu()
6576 		pmu_conf->impl_pmcs[i>>6] |= 1UL << (i&63);  in pfm_init()
6579 	pmu_conf->num_pmcs = n;  in pfm_init()
6584 		pmu_conf->impl_pmds[i>>6] |= 1UL << (i&63);  in pfm_init()
6588 	pmu_conf->num_pmds      = n;  in pfm_init()
6589 	pmu_conf->num_counters  = n_counters;  in pfm_init()
6594 	if (pmu_conf->use_rr_dbregs) {  in pfm_init()
6595 		if (pmu_conf->num_ibrs > IA64_NUM_DBG_REGS) {  in pfm_init()
6596 …printk(KERN_INFO "perfmon: unsupported number of code debug registers (%u)\n", pmu_conf->num_ibrs);  in pfm_init()
6597 			pmu_conf = NULL;  in pfm_init()
6600 		if (pmu_conf->num_dbrs > IA64_NUM_DBG_REGS) {  in pfm_init()
6601 …printk(KERN_INFO "perfmon: unsupported number of data debug registers (%u)\n", pmu_conf->num_ibrs);  in pfm_init()
6602 			pmu_conf = NULL;  in pfm_init()
6608 	       pmu_conf->pmu_name,  in pfm_init()
6609 	       pmu_conf->num_pmcs,  in pfm_init()
6610 	       pmu_conf->num_pmds,  in pfm_init()
6611 	       pmu_conf->num_counters,  in pfm_init()
6612 	       ffz(pmu_conf->ovfl_val));  in pfm_init()
6615 	if (pmu_conf->num_pmds >= PFM_NUM_PMD_REGS || pmu_conf->num_pmcs >= PFM_NUM_PMC_REGS) {  in pfm_init()
6617 		pmu_conf = NULL;  in pfm_init()
6627 		pmu_conf = NULL;  in pfm_init()