28 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_control_bit_clr()  local
33 			__sn_clrq_relaxed(&ptr->tio.cp_control, bits);  in pcireg_control_bit_clr()
36 			__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);  in pcireg_control_bit_clr()
41 			     ptr);  in pcireg_control_bit_clr()
48 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_control_bit_set()  local
53 			__sn_setq_relaxed(&ptr->tio.cp_control, bits);  in pcireg_control_bit_set()
56 			__sn_setq_relaxed(&ptr->pic.p_wid_control, bits);  in pcireg_control_bit_set()
61 			     ptr);  in pcireg_control_bit_set()
71 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_tflush_get()  local
77 			ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);  in pcireg_tflush_get()
80 			ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);  in pcireg_tflush_get()
85 			     ptr);  in pcireg_tflush_get()
101 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_intr_status_get()  local
107 			ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);  in pcireg_intr_status_get()
110 			ret = __sn_readq_relaxed(&ptr->pic.p_int_status);  in pcireg_intr_status_get()
115 			     ptr);  in pcireg_intr_status_get()
126 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_intr_enable_bit_clr()  local
131 			__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);  in pcireg_intr_enable_bit_clr()
134 			__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);  in pcireg_intr_enable_bit_clr()
139 			     ptr);  in pcireg_intr_enable_bit_clr()
146 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_intr_enable_bit_set()  local
151 			__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);  in pcireg_intr_enable_bit_set()
154 			__sn_setq_relaxed(&ptr->pic.p_int_enable, bits);  in pcireg_intr_enable_bit_set()
159 			     ptr);  in pcireg_intr_enable_bit_set()
170 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_intr_addr_addr_set()  local
175 			__sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],  in pcireg_intr_addr_addr_set()
177 			__sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],  in pcireg_intr_addr_addr_set()
181 			__sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],  in pcireg_intr_addr_addr_set()
183 			__sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],  in pcireg_intr_addr_addr_set()
189 			     ptr);  in pcireg_intr_addr_addr_set()
199 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_force_intr_set()  local
204 			writeq(1, &ptr->tio.cp_force_pin[int_n]);  in pcireg_force_intr_set()
207 			writeq(1, &ptr->pic.p_force_pin[int_n]);  in pcireg_force_intr_set()
212 			     ptr);  in pcireg_force_intr_set()
222 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_wrb_flush_get()  local
229 			    __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);  in pcireg_wrb_flush_get()
233 			    __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);  in pcireg_wrb_flush_get()
236 		      panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);  in pcireg_wrb_flush_get()
247 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_int_ate_set()  local
252 			writeq(val, &ptr->tio.cp_int_ate_ram[ate_index]);  in pcireg_int_ate_set()
255 			writeq(val, &ptr->pic.p_int_ate_ram[ate_index]);  in pcireg_int_ate_set()
260 			     ptr);  in pcireg_int_ate_set()
267 	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;  in pcireg_int_ate_addr()  local
273 			ret = &ptr->tio.cp_int_ate_ram[ate_index];  in pcireg_int_ate_addr()
276 			ret = &ptr->pic.p_int_ate_ram[ate_index];  in pcireg_int_ate_addr()
281 			     ptr);  in pcireg_int_ate_addr()