Lines Matching refs:alchemy_rdsys
129 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; in alchemy_clk_cpu_recalc()
182 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; in alchemy_clk_aux_recalc()
266 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; in alchemy_clk_setup_sysbus()
483 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_en()
494 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); in alchemy_clk_fgv1_isen()
505 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_dis()
517 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setp()
532 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
546 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setr()
559 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); in alchemy_clk_fgv1_recalc()
589 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_fgv2_en()
614 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; in alchemy_clk_fgv2_isen()
623 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_dis()
670 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ in alchemy_clk_fgv2_setr()
675 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_setr()
691 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_recalc()
708 if (alchemy_rdsys(c->reg) & (1 << 30)) { in alchemy_clk_fgv2_detr()
790 v = alchemy_rdsys(a->reg); in alchemy_clk_init_fgens()
816 unsigned long v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_isen()
823 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_csrc_en()
850 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_dis()
882 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; in alchemy_clk_csrc_recalc()
911 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_setr()
1013 v = alchemy_rdsys(a->reg); in alchemy_clk_setup_imux()