360 	int shift;		/* offset in register		  */  member
484 	v |= (1 << 1) << c->shift;  in alchemy_clk_fgv1_en()
494 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);  in alchemy_clk_fgv1_isen()
506 	v &= ~((1 << 1) << c->shift);  in alchemy_clk_fgv1_dis()
519 		v |= (1 << c->shift);  in alchemy_clk_fgv1_setp()
521 		v &= ~(1 << c->shift);  in alchemy_clk_fgv1_setp()
532 	return (alchemy_rdsys(c->reg) >> c->shift) & 1;  in alchemy_clk_fgv1_getp()
540 	int sh = c->shift + 2;  in alchemy_clk_fgv1_setr()
559 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);  in alchemy_clk_fgv1_recalc()
591 	v &= ~(3 << c->shift);  in __alchemy_clk_fgv2_en()
592 	v |= (c->parent & 3) << c->shift;  in __alchemy_clk_fgv2_en()
614 	return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;  in alchemy_clk_fgv2_isen()
624 	v &= ~(3 << c->shift);	/* set input mux to "disabled" state */  in alchemy_clk_fgv2_dis()
664 	int sh = c->shift + 2;  in alchemy_clk_fgv2_setr()
688 	int sh = c->shift + 2;  in alchemy_clk_fgv2_recalc()
777 		a->shift = 10 * (i < 3 ? i : i - 3);  in alchemy_clk_init_fgens()
791 			a->parent = (v >> a->shift) & 3;  in alchemy_clk_init_fgens()
818 	return (((v >> c->shift) >> 2) & 7) != 0;  in alchemy_clk_csrc_isen()
825 	v &= ~((7 << 2) << c->shift);  in __alchemy_clk_csrc_en()
826 	v |= ((c->parent & 7) << 2) << c->shift;  in __alchemy_clk_csrc_en()
851 	v &= ~((3 << 2) << c->shift);	/* mux to "disabled" state */  in alchemy_clk_csrc_dis()
882 	unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;  in alchemy_clk_csrc_recalc()
912 	v &= ~(3 << c->shift);  in alchemy_clk_csrc_setr()
913 	v |= (i & 3) << c->shift;  in alchemy_clk_csrc_setr()
1005 		a->shift = i * 5;  in alchemy_clk_setup_imux()
1014 		a->parent = ((v >> a->shift) >> 2) & 7;  in alchemy_clk_setup_imux()