57 	u32 pll;  in ar71xx_clocks_init()  local
63 	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);  in ar71xx_clocks_init()
65 	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;  in ar71xx_clocks_init()
68 	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;  in ar71xx_clocks_init()
71 	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;  in ar71xx_clocks_init()
74 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;  in ar71xx_clocks_init()
92 	u32 pll;  in ar724x_clocks_init()  local
97 	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);  in ar724x_clocks_init()
99 	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);  in ar724x_clocks_init()
102 	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);  in ar724x_clocks_init()
107 	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;  in ar724x_clocks_init()
110 	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;  in ar724x_clocks_init()
128 	u32 pll;  in ar913x_clocks_init()  local
133 	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);  in ar913x_clocks_init()
135 	div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);  in ar913x_clocks_init()
140 	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;  in ar913x_clocks_init()
143 	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;  in ar913x_clocks_init()
243 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;  in ar934x_clocks_init()  local
256 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);  in ar934x_clocks_init()
257 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
258 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
260 		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);  in ar934x_clocks_init()
261 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
263 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
264 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
268 		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);  in ar934x_clocks_init()
269 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
271 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
273 		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
275 		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
283 	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);  in ar934x_clocks_init()
284 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
285 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
287 		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);  in ar934x_clocks_init()
288 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
290 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
291 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
295 		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);  in ar934x_clocks_init()
296 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
298 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
300 		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
302 		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
359 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca955x_clocks_init()  local
369 	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);  in qca955x_clocks_init()
370 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
372 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
374 	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
376 	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()
383 	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);  in qca955x_clocks_init()
384 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
386 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
388 	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
390 	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()