Lines Matching refs:cvmx_write_csr
274 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable()
283 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable()
306 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_enable_local()
315 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_enable_local()
338 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_disable_local()
347 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_disable_local()
378 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_disable_all()
380 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_disable_all()
411 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable_all()
413 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable_all()
438 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_v2()
442 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_v2()
459 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); in octeon_irq_ciu_enable_sum2()
475 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); in octeon_irq_ciu_disable_local_sum2()
488 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask); in octeon_irq_ciu_ack_sum2()
503 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask); in octeon_irq_ciu_disable_all_sum2()
522 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_local_v2()
526 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_local_v2()
541 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_disable_local_v2()
545 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_disable_local_v2()
562 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); in octeon_irq_ciu_ack()
564 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); in octeon_irq_ciu_ack()
586 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_disable_all_v2()
593 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_disable_all_v2()
616 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_enable_all_v2()
623 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_enable_all_v2()
645 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64); in octeon_irq_gpio_setup()
673 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio_v2()
683 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio()
696 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); in octeon_irq_ciu_gpio_ack()
780 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_set_affinity()
782 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_set_affinity()
815 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); in octeon_irq_ciu_set_affinity_v2()
818 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); in octeon_irq_ciu_set_affinity_v2()
828 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); in octeon_irq_ciu_set_affinity_v2()
831 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); in octeon_irq_ciu_set_affinity_v2()
858 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); in octeon_irq_ciu_set_affinity_sum2()
860 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); in octeon_irq_ciu_set_affinity_sum2()
1023 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_wd_enable()
1037 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); in octeon_irq_ciu1_wd_enable_v2()
1345 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1346 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1347 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1348 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1368 cvmx_write_csr(base + regx + ipx, 0); in octeon_irq_init_ciu2_percpu()
1604 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_wd_enable()
1621 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable()
1636 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable_local()
1652 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_local()
1667 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_ack()
1683 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_all()
1697 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_all()
1711 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_all()
1723 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_local()
1734 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_local()
1764 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_set_affinity()
1783 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu2_disable_gpio()
2092 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_enable()
2106 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_disable()
2210 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_handler()
2211 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2219 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2279 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ in octeon_irq_init_cib()
2280 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ in octeon_irq_init_cib()