21 #define dma_outb	outb_p  macro
23 #define dma_outb	outb  macro
175 		dma_outb(dmanr,	 DMA1_MASK_REG);  in enable_dma()
177 		dma_outb(dmanr & 3,  DMA2_MASK_REG);  in enable_dma()
183 		dma_outb(dmanr | 4,  DMA1_MASK_REG);  in disable_dma()
185 		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);  in disable_dma()
198 		dma_outb(0,  DMA1_CLEAR_FF_REG);  in clear_dma_ff()
200 		dma_outb(0,  DMA2_CLEAR_FF_REG);  in clear_dma_ff()
207 		dma_outb(mode | dmanr,	DMA1_MODE_REG);  in set_dma_mode()
209 		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);  in set_dma_mode()
221 			dma_outb(pagenr, DMA_PAGE_0);  in set_dma_page()
224 			dma_outb(pagenr, DMA_PAGE_1);  in set_dma_page()
227 			dma_outb(pagenr, DMA_PAGE_2);  in set_dma_page()
230 			dma_outb(pagenr, DMA_PAGE_3);  in set_dma_page()
233 			dma_outb(pagenr & 0xfe, DMA_PAGE_5);  in set_dma_page()
236 			dma_outb(pagenr & 0xfe, DMA_PAGE_6);  in set_dma_page()
239 			dma_outb(pagenr & 0xfe, DMA_PAGE_7);  in set_dma_page()
252 	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
253 	    dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
255 	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
256 	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
273 	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
274 	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
276 	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()
277 	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()