Lines Matching refs:_ULCAST_
167 #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)
169 #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)
173 #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)
175 #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)
183 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)
187 #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)
189 #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
193 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
195 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)
199 #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)
203 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12)
205 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0)
209 #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17)
211 #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
215 #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17)
217 #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
221 #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
225 #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16)
227 #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5)
229 #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4)
231 #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2)
233 #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0)
234 #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0)
235 #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0)
236 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0)
237 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0)
241 #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
245 #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
249 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
253 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
255 #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0)
259 #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
263 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12)
267 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31)
269 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30)
271 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
273 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1)
275 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0)