57 static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)  in jz4740_irq_set_mask()  argument
59 	struct irq_chip_regs *regs = &gc->chip_types->regs;  in jz4740_irq_set_mask()
61 	writel(mask, gc->reg_base + regs->enable);  in jz4740_irq_set_mask()
62 	writel(~mask, gc->reg_base + regs->disable);  in jz4740_irq_set_mask()
67 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in jz4740_irq_suspend()  local
68 	jz4740_irq_set_mask(gc, gc->wake_active);  in jz4740_irq_suspend()
73 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in jz4740_irq_resume()  local
74 	jz4740_irq_set_mask(gc, gc->mask_cache);  in jz4740_irq_resume()
84 	struct irq_chip_generic *gc;  in arch_init_irq()  local
94 	gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,  in arch_init_irq()
97 	gc->wake_enabled = IRQ_MSK(32);  in arch_init_irq()
99 	ct = gc->chip_types;  in arch_init_irq()
109 	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);  in arch_init_irq()