91 	u64		(*read_counter)(unsigned int idx);
92 	void		(*write_counter)(unsigned int idx, u64 val);
183 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)  in mipsxx_pmu_swizzle_perf_idx()  argument
186 		idx = (idx + 2) & 3;  in mipsxx_pmu_swizzle_perf_idx()
187 	return idx;  in mipsxx_pmu_swizzle_perf_idx()
190 static u64 mipsxx_pmu_read_counter(unsigned int idx)  in mipsxx_pmu_read_counter()  argument
192 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_read_counter()
194 	switch (idx) {  in mipsxx_pmu_read_counter()
208 		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);  in mipsxx_pmu_read_counter()
213 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)  in mipsxx_pmu_read_counter_64()  argument
215 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_read_counter_64()
217 	switch (idx) {  in mipsxx_pmu_read_counter_64()
227 		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);  in mipsxx_pmu_read_counter_64()
232 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)  in mipsxx_pmu_write_counter()  argument
234 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_write_counter()
236 	switch (idx) {  in mipsxx_pmu_write_counter()
252 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)  in mipsxx_pmu_write_counter_64()  argument
254 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_write_counter_64()
256 	switch (idx) {  in mipsxx_pmu_write_counter_64()
272 static unsigned int mipsxx_pmu_read_control(unsigned int idx)  in mipsxx_pmu_read_control()  argument
274 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_read_control()
276 	switch (idx) {  in mipsxx_pmu_read_control()
286 		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);  in mipsxx_pmu_read_control()
291 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)  in mipsxx_pmu_write_control()  argument
293 	idx = mipsxx_pmu_swizzle_perf_idx(idx);  in mipsxx_pmu_write_control()
295 	switch (idx) {  in mipsxx_pmu_write_control()
341 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)  in mipsxx_pmu_enable_event()  argument
345 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipsxx_pmu_enable_event()
347 	cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |  in mipsxx_pmu_enable_event()
353 		cpuc->saved_ctrl[idx] |=  in mipsxx_pmu_enable_event()
361 static void mipsxx_pmu_disable_event(int idx)  in mipsxx_pmu_disable_event()  argument
366 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipsxx_pmu_disable_event()
369 	cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &  in mipsxx_pmu_disable_event()
371 	mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);  in mipsxx_pmu_disable_event()
377 				    int idx)  in mipspmu_event_set_period()  argument
404 	mipspmu.write_counter(idx, mipspmu.overflow - left);  in mipspmu_event_set_period()
413 				 int idx)  in mipspmu_event_update()  argument
420 	new_raw_count = mipspmu.read_counter(idx);  in mipspmu_event_update()
442 	mipspmu_event_set_period(event, hwc, hwc->idx);  in mipspmu_start()
445 	mipsxx_pmu_enable_event(hwc, hwc->idx);  in mipspmu_start()
454 		mipsxx_pmu_disable_event(hwc->idx);  in mipspmu_stop()
456 		mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_stop()
465 	int idx;  in mipspmu_add()  local
471 	idx = mipsxx_pmu_alloc_counter(cpuc, hwc);  in mipspmu_add()
472 	if (idx < 0) {  in mipspmu_add()
473 		err = idx;  in mipspmu_add()
481 	event->hw.idx = idx;  in mipspmu_add()
482 	mipsxx_pmu_disable_event(idx);  in mipspmu_add()
483 	cpuc->events[idx] = event;  in mipspmu_add()
501 	int idx = hwc->idx;  in mipspmu_del()  local
503 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipspmu_del()
506 	cpuc->events[idx] = NULL;  in mipspmu_del()
507 	clear_bit(idx, cpuc->used_mask);  in mipspmu_del()
517 	if (hwc->idx < 0)  in mipspmu_read()
520 	mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_read()
679 static const struct mips_perf_event *mipspmu_map_general_event(int idx)  in mipspmu_map_general_event()  argument
682 	if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)  in mipspmu_map_general_event()
684 	return &(*mipspmu.general_event_map)[idx];  in mipspmu_map_general_event()
739 				    int idx, struct perf_sample_data *data,  in handle_associated_event()  argument
742 	struct perf_event *event = cpuc->events[idx];  in handle_associated_event()
745 	mipspmu_event_update(event, hwc, idx);  in handle_associated_event()
747 	if (!mipspmu_event_set_period(event, hwc, idx))  in handle_associated_event()
751 		mipsxx_pmu_disable_event(idx);  in handle_associated_event()
1319 	hwc->idx = -1;  in __hw_perf_event_init()