21 	u32 hi = 0, lo = value;  in pci_ide_write_reg()  local
25 		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);  in pci_ide_write_reg()
30 		_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);  in pci_ide_write_reg()
34 			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_ide_write_reg()
37 				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_ide_write_reg()
43 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_ide_write_reg()
44 		hi &= 0xffffff00;  in pci_ide_write_reg()
45 		hi |= (value >> 8);  in pci_ide_write_reg()
46 		_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);  in pci_ide_write_reg()
50 			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_ide_write_reg()
52 			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_ide_write_reg()
54 			_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_write_reg()
56 			_wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);  in pci_ide_write_reg()
59 			hi = 0x60000000 | ((value & 0x000ff000) >> 12);  in pci_ide_write_reg()
61 			_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);  in pci_ide_write_reg()
66 			_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);  in pci_ide_write_reg()
68 			_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);  in pci_ide_write_reg()
70 			_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);  in pci_ide_write_reg()
72 			_wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);  in pci_ide_write_reg()
76 		_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);  in pci_ide_write_reg()
78 		_wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);  in pci_ide_write_reg()
81 		_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);  in pci_ide_write_reg()
83 		_wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);  in pci_ide_write_reg()
86 		_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);  in pci_ide_write_reg()
88 		_wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);  in pci_ide_write_reg()
91 		_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);  in pci_ide_write_reg()
93 		_wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);  in pci_ide_write_reg()
103 	u32 hi, lo;  in pci_ide_read_reg()  local
111 		_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_read_reg()
114 		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);  in pci_ide_read_reg()
121 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_ide_read_reg()
127 		_rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);  in pci_ide_read_reg()
132 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_ide_read_reg()
133 		hi &= 0x000000f8;  in pci_ide_read_reg()
134 		conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);  in pci_ide_read_reg()
137 		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_ide_read_reg()
142 			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_ide_read_reg()
144 			_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_read_reg()
168 		_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);  in pci_ide_read_reg()
172 		_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);  in pci_ide_read_reg()
176 		_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);  in pci_ide_read_reg()
180 		_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);  in pci_ide_read_reg()
184 		_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);  in pci_ide_read_reg()