55 	u32 hi, lo;  in divil_lbar_enable()  local
63 		_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);  in divil_lbar_enable()
64 		hi |= 0x01;  in divil_lbar_enable()
65 		_wrmsr(DIVIL_MSR_REG(offset), hi, lo);  in divil_lbar_enable()
74 	u32 hi, lo;  in divil_lbar_disable()  local
78 		_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);  in divil_lbar_disable()
79 		hi &= ~0x01;  in divil_lbar_disable()
80 		_wrmsr(DIVIL_MSR_REG(offset), hi, lo);  in divil_lbar_disable()
90 	u32 hi = 0, lo = value;  in pci_isa_write_bar()  local
93 		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_isa_write_bar()
95 		_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_isa_write_bar()
98 		hi = 0x0000f001;  in pci_isa_write_bar()
100 		_wrmsr(divil_msr_reg[n], hi, lo);  in pci_isa_write_bar()
103 		hi = ((value & 0x000ffffc) << 12) |  in pci_isa_write_bar()
106 		_wrmsr(sb_msr_reg[n], hi, lo);  in pci_isa_write_bar()
117 	u32 hi, lo;  in pci_isa_read_bar()  local
119 	_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_isa_read_bar()
123 		_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_isa_read_bar()
125 		_rdmsr(divil_msr_reg[n], &hi, &lo);  in pci_isa_read_bar()
140 	u32 hi = 0, lo = value;  in pci_isa_write_reg()  local
151 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_write_reg()
170 		_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_isa_write_reg()
174 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_isa_write_reg()
175 		hi &= 0xffffff00;  in pci_isa_write_reg()
176 		hi |= (value >> 8);  in pci_isa_write_reg()
177 		_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);  in pci_isa_write_reg()
198 		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);  in pci_isa_write_reg()
203 		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);  in pci_isa_write_reg()
206 		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);  in pci_isa_write_reg()
211 		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);  in pci_isa_write_reg()
216 			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_write_reg()
218 			_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_isa_write_reg()
235 	u32 hi, lo;  in pci_isa_read_reg()  local
245 		_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);  in pci_isa_read_reg()
246 		if (hi & 0x01)  in pci_isa_read_reg()
254 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_read_reg()
265 		_rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);  in pci_isa_read_reg()
270 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_isa_read_reg()
271 		hi &= 0x000000f8;  in pci_isa_read_reg()
272 		conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);  in pci_isa_read_reg()