Lines Matching refs:dec_insn
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, in isBranchInstr() argument
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn; in isBranchInstr()
450 regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
451 dec_insn.next_pc_inc; in isBranchInstr()
471 dec_insn.pc_inc + in isBranchInstr()
472 dec_insn.next_pc_inc; in isBranchInstr()
480 dec_insn.pc_inc + in isBranchInstr()
484 dec_insn.pc_inc + in isBranchInstr()
485 dec_insn.next_pc_inc; in isBranchInstr()
494 dec_insn.pc_inc + in isBranchInstr()
495 dec_insn.next_pc_inc; in isBranchInstr()
503 dec_insn.pc_inc + in isBranchInstr()
507 dec_insn.pc_inc + in isBranchInstr()
508 dec_insn.next_pc_inc; in isBranchInstr()
516 dec_insn.pc_inc + in isBranchInstr()
517 dec_insn.next_pc_inc; in isBranchInstr()
520 *contpc = regs->cp0_epc + dec_insn.pc_inc; in isBranchInstr()
534 dec_insn.pc_inc + in isBranchInstr()
538 dec_insn.pc_inc + in isBranchInstr()
539 dec_insn.next_pc_inc; in isBranchInstr()
548 dec_insn.pc_inc + in isBranchInstr()
552 dec_insn.pc_inc + in isBranchInstr()
553 dec_insn.next_pc_inc; in isBranchInstr()
577 dec_insn.pc_inc; in isBranchInstr()
578 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
579 dec_insn.next_pc_inc; in isBranchInstr()
585 dec_insn.pc_inc + in isBranchInstr()
589 dec_insn.pc_inc + in isBranchInstr()
590 dec_insn.next_pc_inc; in isBranchInstr()
614 dec_insn.pc_inc; in isBranchInstr()
615 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
616 dec_insn.next_pc_inc; in isBranchInstr()
623 dec_insn.pc_inc + in isBranchInstr()
627 dec_insn.pc_inc + in isBranchInstr()
628 dec_insn.next_pc_inc; in isBranchInstr()
636 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
637 dec_insn.next_pc_inc; in isBranchInstr()
674 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
675 dec_insn.next_pc_inc; in isBranchInstr()
682 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
683 dec_insn.next_pc_inc; in isBranchInstr()
689 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
690 dec_insn.next_pc_inc; in isBranchInstr()
698 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
699 dec_insn.next_pc_inc; in isBranchInstr()
722 dec_insn.pc_inc + in isBranchInstr()
726 dec_insn.pc_inc + in isBranchInstr()
727 dec_insn.next_pc_inc; in isBranchInstr()
750 dec_insn.pc_inc + in isBranchInstr()
754 dec_insn.pc_inc + in isBranchInstr()
755 dec_insn.next_pc_inc; in isBranchInstr()
761 dec_insn.pc_inc + in isBranchInstr()
765 dec_insn.pc_inc + in isBranchInstr()
766 dec_insn.next_pc_inc; in isBranchInstr()
975 struct mm_decoded_insn dec_insn, void *__user *fault_addr) in cop1Emulate() argument
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; in cop1Emulate()
991 if (!cpu_has_mmips && dec_insn.micro_mips_mode) in cop1Emulate()
996 if (dec_insn.micro_mips_mode) { in cop1Emulate()
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
1000 if (!isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
1018 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1019 pc_inc = dec_insn.next_pc_inc; in cop1Emulate()
1021 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1022 pc_inc = dec_insn.pc_inc; in cop1Emulate()
1035 if (dec_insn.micro_mips_mode) { in cop1Emulate()
1244 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1247 ir = dec_insn.next_insn; in cop1Emulate()
1248 if (dec_insn.micro_mips_mode) { in cop1Emulate()
1252 if ((dec_insn.next_pc_inc == 2) || in cop1Emulate()
1262 if (dec_insn.next_pc_inc == 2) in cop1Emulate()
1333 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1334 contpc += dec_insn.pc_inc; in cop1Emulate()
2147 struct mm_decoded_insn dec_insn; in fpu_emulator_cop1Handler() local
2173 dec_insn.insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2176 dec_insn.pc_inc = 2; in fpu_emulator_cop1Handler()
2179 dec_insn.insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2182 dec_insn.pc_inc = 4; in fpu_emulator_cop1Handler()
2188 dec_insn.next_insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2191 dec_insn.next_pc_inc = 2; in fpu_emulator_cop1Handler()
2193 dec_insn.next_insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2196 dec_insn.next_pc_inc = 4; in fpu_emulator_cop1Handler()
2198 dec_insn.micro_mips_mode = 1; in fpu_emulator_cop1Handler()
2200 if ((get_user(dec_insn.insn, in fpu_emulator_cop1Handler()
2202 (get_user(dec_insn.next_insn, in fpu_emulator_cop1Handler()
2207 dec_insn.pc_inc = 4; in fpu_emulator_cop1Handler()
2208 dec_insn.next_pc_inc = 4; in fpu_emulator_cop1Handler()
2209 dec_insn.micro_mips_mode = 0; in fpu_emulator_cop1Handler()
2212 if ((dec_insn.insn == 0) || in fpu_emulator_cop1Handler()
2213 ((dec_insn.pc_inc == 2) && in fpu_emulator_cop1Handler()
2214 ((dec_insn.insn & 0xffff) == MM_NOP16))) in fpu_emulator_cop1Handler()
2215 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ in fpu_emulator_cop1Handler()
2221 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); in fpu_emulator_cop1Handler()