Lines Matching refs:ir
852 mips_instruction ir) in cop1_cfc() argument
857 switch (MIPSInst_RD(ir)) { in cop1_cfc()
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
901 if (MIPSInst_RT(ir)) in cop1_cfc()
902 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
909 mips_instruction ir) in cop1_ctc() argument
915 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
918 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
920 switch (MIPSInst_RD(ir)) { in cop1_ctc()
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
979 mips_instruction ir; in cop1Emulate() local
1018 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1021 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) in cop1Emulate()
1050 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1053 MIPSInst_SIMM(ir)); in cop1Emulate()
1066 DITOREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1071 MIPSInst_SIMM(ir)); in cop1Emulate()
1073 DIFROMREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1088 MIPSInst_SIMM(ir)); in cop1Emulate()
1100 SITOREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1105 MIPSInst_SIMM(ir)); in cop1Emulate()
1107 SIFROMREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1121 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1127 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1129 MIPSInst_RD(ir)); in cop1Emulate()
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1146 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1148 MIPSInst_RD(ir)); in cop1Emulate()
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1162 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1164 MIPSInst_RD(ir)); in cop1Emulate()
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1175 cop1_cfc(xcp, ctx, ir); in cop1Emulate()
1180 cop1_ctc(xcp, ctx, ir); in cop1Emulate()
1192 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1) in cop1Emulate()
1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)) in cop1Emulate()
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1215 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
1246 contpc = MIPSInst_SIMM(ir); in cop1Emulate()
1247 ir = dec_insn.next_insn; in cop1Emulate()
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { in cop1Emulate()
1263 ir = (ir & (~0xffff)) | MM_NOP16; in cop1Emulate()
1269 sig = mips_dsemul(xcp, ir, in cop1Emulate()
1282 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1305 switch (MIPSInst_FUNC(ir)) { in cop1Emulate()
1323 sig = mips_dsemul(xcp, ir, contpc); in cop1Emulate()
1343 if (!(MIPSInst_RS(ir) & 0x10)) in cop1Emulate()
1347 if ((sig = fpu_emu(xcp, ctx, ir))) in cop1Emulate()
1356 sig = fpux_emu(xcp, ctx, ir, fault_addr); in cop1Emulate()
1365 if (MIPSInst_FUNC(ir) != movc_op) in cop1Emulate()
1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()
1369 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
1370 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
1450 mips_instruction ir, void *__user *fault_addr) in fpux_emu() argument
1456 switch (MIPSInst_FMA_FFMT(ir)) { in fpux_emu()
1464 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1466 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1467 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1480 SITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1484 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1485 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1489 SIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1516 SPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1517 SPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1518 SPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1520 SPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1561 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1563 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1564 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1577 DITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1581 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1582 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1585 DIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1612 DPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1613 DPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1614 DPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1616 DPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1626 if (MIPSInst_FUNC(ir) != pfetch_op) in fpux_emu()
1645 mips_instruction ir) in fpu_emu() argument
1661 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { in fpu_emu()
1669 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
1715 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
1717 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
1719 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1726 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1728 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1735 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1737 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1750 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1755 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1756 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1761 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1792 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1798 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1811 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1812 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1822 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1835 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1836 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1843 if (MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
1844 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
1847 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1848 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1872 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
1915 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
1917 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
1919 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
1925 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1927 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
1933 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1935 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
1947 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
1952 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1953 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1958 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1966 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1975 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1988 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1989 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1999 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2012 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2013 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2020 if (MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
2021 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
2024 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2025 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2046 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2049 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2055 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2070 DIFROMREG(bits, MIPSInst_FS(ir)); in fpu_emu()
2072 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2112 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; in fpu_emu()
2122 DPTOREG(rv.d, MIPSInst_FD(ir)); in fpu_emu()
2125 SPTOREG(rv.s, MIPSInst_FD(ir)); in fpu_emu()
2128 SITOREG(rv.w, MIPSInst_FD(ir)); in fpu_emu()
2134 DITOREG(rv.l, MIPSInst_FD(ir)); in fpu_emu()