967 		union cvmx_npei_ctl_port1 npei_ctl_port;  in __cvmx_pcie_rc_initialize_gen1()  local
968 		npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);  in __cvmx_pcie_rc_initialize_gen1()
969 		npei_ctl_port.s.bar2_enb = 1;  in __cvmx_pcie_rc_initialize_gen1()
970 		npei_ctl_port.s.bar2_esx = 1;  in __cvmx_pcie_rc_initialize_gen1()
971 		npei_ctl_port.s.bar2_cax = 0;  in __cvmx_pcie_rc_initialize_gen1()
972 		npei_ctl_port.s.ptlp_ro = 1;  in __cvmx_pcie_rc_initialize_gen1()
973 		npei_ctl_port.s.ctlp_ro = 1;  in __cvmx_pcie_rc_initialize_gen1()
974 		npei_ctl_port.s.wait_com = 0;  in __cvmx_pcie_rc_initialize_gen1()
975 		npei_ctl_port.s.waitl_com = 0;  in __cvmx_pcie_rc_initialize_gen1()
976 		cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);  in __cvmx_pcie_rc_initialize_gen1()
978 		union cvmx_npei_ctl_port0 npei_ctl_port;  in __cvmx_pcie_rc_initialize_gen1()  local
979 		npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);  in __cvmx_pcie_rc_initialize_gen1()
980 		npei_ctl_port.s.bar2_enb = 1;  in __cvmx_pcie_rc_initialize_gen1()
981 		npei_ctl_port.s.bar2_esx = 1;  in __cvmx_pcie_rc_initialize_gen1()
982 		npei_ctl_port.s.bar2_cax = 0;  in __cvmx_pcie_rc_initialize_gen1()
983 		npei_ctl_port.s.ptlp_ro = 1;  in __cvmx_pcie_rc_initialize_gen1()
984 		npei_ctl_port.s.ctlp_ro = 1;  in __cvmx_pcie_rc_initialize_gen1()
985 		npei_ctl_port.s.wait_com = 0;  in __cvmx_pcie_rc_initialize_gen1()
986 		npei_ctl_port.s.waitl_com = 0;  in __cvmx_pcie_rc_initialize_gen1()
987 		cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);  in __cvmx_pcie_rc_initialize_gen1()