269 	struct eeh_pe *pe = data;  in eeh_dump_pe_log()  local
277 	if (pe->state & EEH_PE_CFG_BLOCKED)  in eeh_dump_pe_log()
280 	eeh_pe_for_each_dev(pe, edev, tmp)  in eeh_dump_pe_log()
297 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)  in eeh_slot_error_detail()  argument
310 	if (!(pe->type & EEH_PE_PHB)) {  in eeh_slot_error_detail()
312 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);  in eeh_slot_error_detail()
326 		eeh_ops->configure_bridge(pe);  in eeh_slot_error_detail()
327 		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {  in eeh_slot_error_detail()
328 			eeh_pe_restore_bars(pe);  in eeh_slot_error_detail()
331 			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);  in eeh_slot_error_detail()
335 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);  in eeh_slot_error_detail()
370 static int eeh_phb_check_failure(struct eeh_pe *pe)  in eeh_phb_check_failure()  argument
380 	phb_pe = eeh_phb_pe_get(pe->phb);  in eeh_phb_check_failure()
383 			__func__, pe->phb->global_number);  in eeh_phb_check_failure()
440 	struct eeh_pe *pe, *parent_pe, *phb_pe;  in eeh_dev_check_failure()  local
454 	pe = eeh_dev_to_pe(edev);  in eeh_dev_check_failure()
457 	if (!pe) {  in eeh_dev_check_failure()
464 	if (!pe->addr && !pe->config_addr) {  in eeh_dev_check_failure()
473 	ret = eeh_phb_check_failure(pe);  in eeh_dev_check_failure()
482 	if (eeh_pe_passed(pe))  in eeh_dev_check_failure()
493 	if (pe->state & EEH_PE_ISOLATED) {  in eeh_dev_check_failure()
494 		pe->check_count++;  in eeh_dev_check_failure()
495 		if (pe->check_count % EEH_MAX_FAILS == 0) {  in eeh_dev_check_failure()
501 				pe->check_count,  in eeh_dev_check_failure()
518 	ret = eeh_ops->get_state(pe, NULL);  in eeh_dev_check_failure()
530 		pe->false_positives++;  in eeh_dev_check_failure()
540 	parent_pe = pe->parent;  in eeh_dev_check_failure()
550 			pe = parent_pe;  in eeh_dev_check_failure()
562 	eeh_pe_state_mark(pe, EEH_PE_ISOLATED);  in eeh_dev_check_failure()
569 	phb_pe = eeh_phb_pe_get(pe->phb);  in eeh_dev_check_failure()
571 	       pe->phb->global_number, pe->addr);  in eeh_dev_check_failure()
573 	       eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));  in eeh_dev_check_failure()
576 	eeh_send_failure_event(pe);  in eeh_dev_check_failure()
624 int eeh_pci_enable(struct eeh_pe *pe, int function)  in eeh_pci_enable()  argument
656 		rc = eeh_ops->get_state(pe, NULL);  in eeh_pci_enable()
671 	rc = eeh_ops->set_option(pe, function);  in eeh_pci_enable()
675 			__func__, function, pe->phb->global_number,  in eeh_pci_enable()
676 			pe->addr, rc);  in eeh_pci_enable()
680 		rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_pci_enable()
753 	struct eeh_pe *pe = eeh_dev_to_pe(edev);  in pcibios_set_pcie_reset_state()  local
755 	if (!pe) {  in pcibios_set_pcie_reset_state()
763 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in pcibios_set_pcie_reset_state()
764 		eeh_unfreeze_pe(pe, false);  in pcibios_set_pcie_reset_state()
765 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
766 		eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);  in pcibios_set_pcie_reset_state()
767 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED);  in pcibios_set_pcie_reset_state()
770 		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);  in pcibios_set_pcie_reset_state()
771 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
772 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);  in pcibios_set_pcie_reset_state()
773 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
774 		eeh_ops->reset(pe, EEH_RESET_HOT);  in pcibios_set_pcie_reset_state()
777 		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);  in pcibios_set_pcie_reset_state()
778 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
779 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);  in pcibios_set_pcie_reset_state()
780 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
781 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in pcibios_set_pcie_reset_state()
784 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
820 static void eeh_reset_pe_once(struct eeh_pe *pe)  in eeh_reset_pe_once()  argument
830 	eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);  in eeh_reset_pe_once()
833 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in eeh_reset_pe_once()
835 		eeh_ops->reset(pe, EEH_RESET_HOT);  in eeh_reset_pe_once()
837 	eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in eeh_reset_pe_once()
848 int eeh_reset_pe(struct eeh_pe *pe)  in eeh_reset_pe()  argument
854 	eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);  in eeh_reset_pe()
858 		eeh_reset_pe_once(pe);  in eeh_reset_pe()
864 		state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_reset_pe()
872 				__func__, pe->phb->global_number, pe->addr);  in eeh_reset_pe()
880 			__func__, state, pe->phb->global_number, pe->addr, (i + 1));  in eeh_reset_pe()
884 	eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);  in eeh_reset_pe()
1235 	if (!edev || !edev->pdev || !edev->pe) {  in eeh_remove_device()
1248 	if (!(edev->pe->state & EEH_PE_KEEP))  in eeh_remove_device()
1266 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)  in eeh_unfreeze_pe()  argument
1270 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);  in eeh_unfreeze_pe()
1273 			__func__, ret, pe->phb->global_number, pe->addr);  in eeh_unfreeze_pe()
1277 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);  in eeh_unfreeze_pe()
1280 			__func__, ret, pe->phb->global_number, pe->addr);  in eeh_unfreeze_pe()
1285 	if (sw_state && (pe->state & EEH_PE_ISOLATED))  in eeh_unfreeze_pe()
1286 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED);  in eeh_unfreeze_pe()
1299 static int eeh_pe_change_owner(struct eeh_pe *pe)  in eeh_pe_change_owner()  argument
1308 	ret = eeh_ops->get_state(pe, NULL);  in eeh_pe_change_owner()
1317 	eeh_pe_for_each_dev(pe, edev, tmp) {  in eeh_pe_change_owner()
1340 	return eeh_unfreeze_pe(pe, true);  in eeh_pe_change_owner()
1343 	return eeh_pe_reset_and_recover(pe);  in eeh_pe_change_owner()
1368 	if (!edev || !edev->pe)  in eeh_dev_open()
1377 	ret = eeh_pe_change_owner(edev->pe);  in eeh_dev_open()
1382 	atomic_inc(&edev->pe->pass_dev_cnt);  in eeh_dev_open()
1412 	if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))  in eeh_dev_release()
1416 	atomic_dec(&edev->pe->pass_dev_cnt);  in eeh_dev_release()
1417 	WARN_ON(atomic_read(&edev->pe->pass_dev_cnt) < 0);  in eeh_dev_release()
1418 	eeh_pe_change_owner(edev->pe);  in eeh_dev_release()
1466 	if (!edev || !edev->pe)  in eeh_iommu_group_to_pe()
1469 	return edev->pe;  in eeh_iommu_group_to_pe()
1483 int eeh_pe_set_option(struct eeh_pe *pe, int option)  in eeh_pe_set_option()  argument
1488 	if (!pe)  in eeh_pe_set_option()
1499 			ret = eeh_pe_change_owner(pe);  in eeh_pe_set_option()
1513 		ret = eeh_pci_enable(pe, option);  in eeh_pe_set_option()
1532 int eeh_pe_get_state(struct eeh_pe *pe)  in eeh_pe_get_state()  argument
1538 	if (!pe)  in eeh_pe_get_state()
1544 	result = eeh_ops->get_state(pe, NULL);  in eeh_pe_get_state()
1564 static int eeh_pe_reenable_devices(struct eeh_pe *pe)  in eeh_pe_reenable_devices()  argument
1571 	eeh_pe_restore_bars(pe);  in eeh_pe_reenable_devices()
1577 	eeh_pe_for_each_dev(pe, edev, tmp) {  in eeh_pe_reenable_devices()
1591 	return eeh_unfreeze_pe(pe, true);  in eeh_pe_reenable_devices()
1603 int eeh_pe_reset(struct eeh_pe *pe, int option)  in eeh_pe_reset()  argument
1608 	if (!pe)  in eeh_pe_reset()
1616 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1617 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);  in eeh_pe_reset()
1621 		ret = eeh_pe_reenable_devices(pe);  in eeh_pe_reset()
1630 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in eeh_pe_reset()
1632 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in eeh_pe_reset()
1633 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1653 int eeh_pe_configure(struct eeh_pe *pe)  in eeh_pe_configure()  argument
1658 	if (!pe)  in eeh_pe_configure()