129 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
172 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)  argument
242 static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst,  in mpic_irq_raise()  argument
251 			 __func__, (int)(dst - &opp->dst[0]));  in mpic_irq_raise()
264 static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst,  in mpic_irq_lower()  argument
269 			 __func__, (int)(dst - &opp->dst[0]));  in mpic_irq_lower()
292 static void IRQ_check(struct openpic *opp, struct irq_queue *q)  in IRQ_check()  argument
299 		irq = find_next_bit(q->queue, opp->max_irq, irq + 1);  in IRQ_check()
300 		if (irq == opp->max_irq)  in IRQ_check()
304 			irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);  in IRQ_check()
306 		if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {  in IRQ_check()
308 			priority = IVPR_PRIORITY(opp->src[irq].ivpr);  in IRQ_check()
316 static int IRQ_get_next(struct openpic *opp, struct irq_queue *q)  in IRQ_get_next()  argument
319 	IRQ_check(opp, q);  in IRQ_get_next()
324 static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,  in IRQ_local_pipe()  argument
331 	dst = &opp->dst[n_CPU];  in IRQ_local_pipe()
332 	src = &opp->src[n_IRQ];  in IRQ_local_pipe()
351 				mpic_irq_raise(opp, dst, src->output);  in IRQ_local_pipe()
358 				mpic_irq_lower(opp, dst, src->output);  in IRQ_local_pipe()
375 	IRQ_check(opp, &dst->raised);  in IRQ_local_pipe()
384 		if (IRQ_get_next(opp, &dst->servicing) >= 0 &&  in IRQ_local_pipe()
391 			mpic_irq_raise(opp, dst, ILR_INTTGT_INT);  in IRQ_local_pipe()
394 		IRQ_get_next(opp, &dst->servicing);  in IRQ_local_pipe()
406 			mpic_irq_lower(opp, dst, ILR_INTTGT_INT);  in IRQ_local_pipe()
412 static void openpic_update_irq(struct openpic *opp, int n_IRQ)  in openpic_update_irq()  argument
418 	src = &opp->src[n_IRQ];  in openpic_update_irq()
451 		IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);  in openpic_update_irq()
454 		for (i = 0; i < opp->nb_cpus; i++) {  in openpic_update_irq()
456 				IRQ_local_pipe(opp, i, n_IRQ, active,  in openpic_update_irq()
463 			if (i == opp->nb_cpus)  in openpic_update_irq()
467 				IRQ_local_pipe(opp, i, n_IRQ, active,  in openpic_update_irq()
478 	struct openpic *opp = opaque;  in openpic_set_irq()  local
486 	src = &opp->src[n_IRQ];  in openpic_set_irq()
492 		openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
497 			openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
508 			openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
513 static void openpic_reset(struct openpic *opp)  in openpic_reset()  argument
517 	opp->gcr = GCR_RESET;  in openpic_reset()
519 	opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |  in openpic_reset()
520 	    (opp->vid << FRR_VID_SHIFT);  in openpic_reset()
522 	opp->pir = 0;  in openpic_reset()
523 	opp->spve = -1 & opp->vector_mask;  in openpic_reset()
524 	opp->tfrr = opp->tfrr_reset;  in openpic_reset()
526 	for (i = 0; i < opp->max_irq; i++) {  in openpic_reset()
527 		opp->src[i].ivpr = opp->ivpr_reset;  in openpic_reset()
529 		switch (opp->src[i].type) {  in openpic_reset()
531 			opp->src[i].level =  in openpic_reset()
532 			    !!(opp->ivpr_reset & IVPR_SENSE_MASK);  in openpic_reset()
536 			opp->src[i].ivpr |= IVPR_POLARITY_MASK;  in openpic_reset()
543 		write_IRQreg_idr(opp, i, opp->idr_reset);  in openpic_reset()
547 		opp->dst[i].ctpr = 15;  in openpic_reset()
548 		memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue));  in openpic_reset()
549 		opp->dst[i].raised.next = -1;  in openpic_reset()
550 		memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue));  in openpic_reset()
551 		opp->dst[i].servicing.next = -1;  in openpic_reset()
555 		opp->timers[i].tccr = 0;  in openpic_reset()
556 		opp->timers[i].tbcr = TBCR_CI;  in openpic_reset()
559 	opp->gcr = 0;  in openpic_reset()
562 static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)  in read_IRQreg_idr()  argument
564 	return opp->src[n_IRQ].idr;  in read_IRQreg_idr()
567 static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)  in read_IRQreg_ilr()  argument
569 	if (opp->flags & OPENPIC_FLAG_ILR)  in read_IRQreg_ilr()
570 		return opp->src[n_IRQ].output;  in read_IRQreg_ilr()
575 static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)  in read_IRQreg_ivpr()  argument
577 	return opp->src[n_IRQ].ivpr;  in read_IRQreg_ivpr()
580 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,  in write_IRQreg_idr()  argument
583 	struct irq_source *src = &opp->src[n_IRQ];  in write_IRQreg_idr()
584 	uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;  in write_IRQreg_idr()
587 	int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;  in write_IRQreg_idr()
590 	if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {  in write_IRQreg_idr()
598 	if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {  in write_IRQreg_idr()
609 			for (i = 0; i < opp->nb_cpus; i++) {  in write_IRQreg_idr()
625 static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,  in write_IRQreg_ilr()  argument
628 	if (opp->flags & OPENPIC_FLAG_ILR) {  in write_IRQreg_ilr()
629 		struct irq_source *src = &opp->src[n_IRQ];  in write_IRQreg_ilr()
639 static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,  in write_IRQreg_ivpr()  argument
648 	    IVPR_POLARITY_MASK | opp->vector_mask;  in write_IRQreg_ivpr()
651 	opp->src[n_IRQ].ivpr =  in write_IRQreg_ivpr()
652 	    (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);  in write_IRQreg_ivpr()
658 	switch (opp->src[n_IRQ].type) {  in write_IRQreg_ivpr()
660 		opp->src[n_IRQ].level =  in write_IRQreg_ivpr()
661 		    !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);  in write_IRQreg_ivpr()
665 		opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;  in write_IRQreg_ivpr()
669 		opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);  in write_IRQreg_ivpr()
673 	openpic_update_irq(opp, n_IRQ);  in write_IRQreg_ivpr()
675 		opp->src[n_IRQ].ivpr);  in write_IRQreg_ivpr()
678 static void openpic_gcr_write(struct openpic *opp, uint64_t val)  in openpic_gcr_write()  argument
681 		openpic_reset(opp);  in openpic_gcr_write()
685 	opp->gcr &= ~opp->mpic_mode_mask;  in openpic_gcr_write()
686 	opp->gcr |= val & opp->mpic_mode_mask;  in openpic_gcr_write()
691 	struct openpic *opp = opaque;  in openpic_gbl_write()  local
709 		err = openpic_cpu_write_internal(opp, addr, val,  in openpic_gbl_write()
715 		openpic_gcr_write(opp, val);  in openpic_gbl_write()
732 		write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);  in openpic_gbl_write()
736 		opp->spve = val & opp->vector_mask;  in openpic_gbl_write()
747 	struct openpic *opp = opaque;  in openpic_gbl_read()  local
758 		retval = opp->frr;  in openpic_gbl_read()
759 		retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT;  in openpic_gbl_read()
762 		retval = opp->gcr;  in openpic_gbl_read()
765 		retval = opp->vir;  in openpic_gbl_read()
771 		retval = opp->brr1;  in openpic_gbl_read()
781 		err = openpic_cpu_read_internal(opp, addr,  in openpic_gbl_read()
791 			retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);  in openpic_gbl_read()
795 		retval = opp->spve;  in openpic_gbl_read()
809 	struct openpic *opp = opaque;  in openpic_tmr_write()  local
820 		opp->tfrr = val;  in openpic_tmr_write()
831 		if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&  in openpic_tmr_write()
833 		    (opp->timers[idx].tbcr & TBCR_CI) != 0)  in openpic_tmr_write()
834 			opp->timers[idx].tccr &= ~TCCR_TOG;  in openpic_tmr_write()
836 		opp->timers[idx].tbcr = val;  in openpic_tmr_write()
839 		write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);  in openpic_tmr_write()
842 		write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);  in openpic_tmr_write()
851 	struct openpic *opp = opaque;  in openpic_tmr_read()  local
862 		retval = opp->tfrr;  in openpic_tmr_read()
868 		retval = opp->timers[idx].tccr;  in openpic_tmr_read()
871 		retval = opp->timers[idx].tbcr;  in openpic_tmr_read()
874 		retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);  in openpic_tmr_read()
877 		retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);  in openpic_tmr_read()
889 	struct openpic *opp = opaque;  in openpic_src_write()  local
899 		write_IRQreg_ivpr(opp, idx, val);  in openpic_src_write()
902 		write_IRQreg_idr(opp, idx, val);  in openpic_src_write()
905 		write_IRQreg_ilr(opp, idx, val);  in openpic_src_write()
914 	struct openpic *opp = opaque;  in openpic_src_read()  local
926 		retval = read_IRQreg_ivpr(opp, idx);  in openpic_src_read()
929 		retval = read_IRQreg_idr(opp, idx);  in openpic_src_read()
932 		retval = read_IRQreg_ilr(opp, idx);  in openpic_src_read()
943 	struct openpic *opp = opaque;  in openpic_msi_write()  local
944 	int idx = opp->irq_msi;  in openpic_msi_write()
956 		opp->msi[srs].msir |= 1 << ibs;  in openpic_msi_write()
957 		openpic_set_irq(opp, idx, 1);  in openpic_msi_write()
969 	struct openpic *opp = opaque;  in openpic_msi_read()  local
988 		r = opp->msi[srs].msir;  in openpic_msi_read()
990 		opp->msi[srs].msir = 0;  in openpic_msi_read()
991 		openpic_set_irq(opp, opp->irq_msi + srs, 0);  in openpic_msi_read()
995 			r |= (opp->msi[i].msir ? 1 : 0) << i;  in openpic_msi_read()
1027 	struct openpic *opp = opaque;  in openpic_cpu_write_internal()  local
1041 	dst = &opp->dst[idx];  in openpic_cpu_write_internal()
1050 		opp->src[opp->irq_ipi0 + idx].destmask |= val;  in openpic_cpu_write_internal()
1051 		openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);  in openpic_cpu_write_internal()
1052 		openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);  in openpic_cpu_write_internal()
1064 			mpic_irq_lower(opp, dst, ILR_INTTGT_INT);  in openpic_cpu_write_internal()
1068 			mpic_irq_raise(opp, dst, ILR_INTTGT_INT);  in openpic_cpu_write_internal()
1082 		s_IRQ = IRQ_get_next(opp, &dst->servicing);  in openpic_cpu_write_internal()
1094 		s_IRQ = IRQ_get_next(opp, &dst->servicing);  in openpic_cpu_write_internal()
1096 		n_IRQ = IRQ_get_next(opp, &dst->raised);  in openpic_cpu_write_internal()
1097 		src = &opp->src[n_IRQ];  in openpic_cpu_write_internal()
1103 			mpic_irq_raise(opp, dst, ILR_INTTGT_INT);  in openpic_cpu_write_internal()
1106 		spin_unlock(&opp->lock);  in openpic_cpu_write_internal()
1107 		kvm_notify_acked_irq(opp->kvm, 0, notify_eoi);  in openpic_cpu_write_internal()
1108 		spin_lock(&opp->lock);  in openpic_cpu_write_internal()
1121 	struct openpic *opp = opaque;  in openpic_cpu_write()  local
1123 	return openpic_cpu_write_internal(opp, addr, val,  in openpic_cpu_write()
1127 static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst,  in openpic_iack()  argument
1134 	mpic_irq_lower(opp, dst, ILR_INTTGT_INT);  in openpic_iack()
1136 	irq = IRQ_get_next(opp, &dst->raised);  in openpic_iack()
1141 		return opp->spve;  in openpic_iack()
1143 	src = &opp->src[irq];  in openpic_iack()
1148 		openpic_update_irq(opp, irq);  in openpic_iack()
1149 		retval = opp->spve;  in openpic_iack()
1153 		retval = IVPR_VECTOR(opp, src->ivpr);  in openpic_iack()
1163 	if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) {  in openpic_iack()
1167 			openpic_set_irq(opp, irq, 1);  in openpic_iack()
1168 			openpic_set_irq(opp, irq, 0);  in openpic_iack()
1179 	struct openpic *opp = vcpu->arch.mpic;  in kvmppc_mpic_set_epr()  local
1183 	spin_lock_irqsave(&opp->lock, flags);  in kvmppc_mpic_set_epr()
1185 	if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY)  in kvmppc_mpic_set_epr()
1186 		kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu));  in kvmppc_mpic_set_epr()
1188 	spin_unlock_irqrestore(&opp->lock, flags);  in kvmppc_mpic_set_epr()
1194 	struct openpic *opp = opaque;  in openpic_cpu_read_internal()  local
1207 	dst = &opp->dst[idx];  in openpic_cpu_read_internal()
1217 		retval = openpic_iack(opp, dst, idx);  in openpic_cpu_read_internal()
1234 	struct openpic *opp = opaque;  in openpic_cpu_read()  local
1236 	return openpic_cpu_read_internal(opp, addr, ptr,  in openpic_cpu_read()
1289 static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)  in add_mmio_region()  argument
1291 	if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) {  in add_mmio_region()
1296 	opp->mmio_regions[opp->num_mmio_regions++] = mr;  in add_mmio_region()
1299 static void fsl_common_init(struct openpic *opp)  in fsl_common_init()  argument
1304 	add_mmio_region(opp, &openpic_msi_mmio);  in fsl_common_init()
1305 	add_mmio_region(opp, &openpic_summary_mmio);  in fsl_common_init()
1307 	opp->vid = VID_REVISION_1_2;  in fsl_common_init()
1308 	opp->vir = VIR_GENERIC;  in fsl_common_init()
1309 	opp->vector_mask = 0xFFFF;  in fsl_common_init()
1310 	opp->tfrr_reset = 0;  in fsl_common_init()
1311 	opp->ivpr_reset = IVPR_MASK_MASK;  in fsl_common_init()
1312 	opp->idr_reset = 1 << 0;  in fsl_common_init()
1313 	opp->max_irq = MAX_IRQ;  in fsl_common_init()
1315 	opp->irq_ipi0 = virq;  in fsl_common_init()
1317 	opp->irq_tim0 = virq;  in fsl_common_init()
1322 	opp->irq_msi = 224;  in fsl_common_init()
1324 	for (i = 0; i < opp->fsl->max_ext; i++)  in fsl_common_init()
1325 		opp->src[i].level = false;  in fsl_common_init()
1329 		opp->src[i].type = IRQ_TYPE_FSLINT;  in fsl_common_init()
1330 		opp->src[i].level = true;  in fsl_common_init()
1335 		opp->src[i].type = IRQ_TYPE_FSLSPECIAL;  in fsl_common_init()
1336 		opp->src[i].level = false;  in fsl_common_init()
1340 static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr)  in kvm_mpic_read_internal()  argument
1344 	for (i = 0; i < opp->num_mmio_regions; i++) {  in kvm_mpic_read_internal()
1345 		const struct mem_reg *mr = opp->mmio_regions[i];  in kvm_mpic_read_internal()
1350 		return mr->read(opp, addr - mr->start_addr, ptr);  in kvm_mpic_read_internal()
1356 static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)  in kvm_mpic_write_internal()  argument
1360 	for (i = 0; i < opp->num_mmio_regions; i++) {  in kvm_mpic_write_internal()
1361 		const struct mem_reg *mr = opp->mmio_regions[i];  in kvm_mpic_write_internal()
1366 		return mr->write(opp, addr - mr->start_addr, val);  in kvm_mpic_write_internal()
1376 	struct openpic *opp = container_of(this, struct openpic, mmio);  in kvm_mpic_read()  local
1389 	spin_lock_irq(&opp->lock);  in kvm_mpic_read()
1390 	ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);  in kvm_mpic_read()
1391 	spin_unlock_irq(&opp->lock);  in kvm_mpic_read()
1418 	struct openpic *opp = container_of(this, struct openpic, mmio);  in kvm_mpic_write()  local
1430 	spin_lock_irq(&opp->lock);  in kvm_mpic_write()
1431 	ret = kvm_mpic_write_internal(opp, addr - opp->reg_base,  in kvm_mpic_write()
1433 	spin_unlock_irq(&opp->lock);  in kvm_mpic_write()
1446 static void map_mmio(struct openpic *opp)  in map_mmio()  argument
1448 	kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops);  in map_mmio()
1450 	kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS,  in map_mmio()
1451 				opp->reg_base, OPENPIC_REG_SIZE,  in map_mmio()
1452 				&opp->mmio);  in map_mmio()
1455 static void unmap_mmio(struct openpic *opp)  in unmap_mmio()  argument
1457 	kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio);  in unmap_mmio()
1460 static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr)  in set_base_addr()  argument
1473 	if (base == opp->reg_base)  in set_base_addr()
1476 	mutex_lock(&opp->kvm->slots_lock);  in set_base_addr()
1478 	unmap_mmio(opp);  in set_base_addr()
1479 	opp->reg_base = base;  in set_base_addr()
1487 	map_mmio(opp);  in set_base_addr()
1490 	mutex_unlock(&opp->kvm->slots_lock);  in set_base_addr()
1497 static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)  in access_reg()  argument
1504 	spin_lock_irq(&opp->lock);  in access_reg()
1507 		ret = kvm_mpic_write_internal(opp, addr, *val);  in access_reg()
1509 		ret = kvm_mpic_read_internal(opp, addr, val);  in access_reg()
1511 	spin_unlock_irq(&opp->lock);  in access_reg()
1520 	struct openpic *opp = dev->private;  in mpic_set_attr()  local
1527 			return set_base_addr(opp, attr);  in mpic_set_attr()
1536 		return access_reg(opp, attr->attr, &attr32, ATTR_SET);  in mpic_set_attr()
1548 		spin_lock_irq(&opp->lock);  in mpic_set_attr()
1549 		openpic_set_irq(opp, attr->attr, attr32);  in mpic_set_attr()
1550 		spin_unlock_irq(&opp->lock);  in mpic_set_attr()
1559 	struct openpic *opp = dev->private;  in mpic_get_attr()  local
1568 			mutex_lock(&opp->kvm->slots_lock);  in mpic_get_attr()
1569 			attr64 = opp->reg_base;  in mpic_get_attr()
1570 			mutex_unlock(&opp->kvm->slots_lock);  in mpic_get_attr()
1582 		ret = access_reg(opp, attr->attr, &attr32, ATTR_GET);  in mpic_get_attr()
1595 		spin_lock_irq(&opp->lock);  in mpic_get_attr()
1596 		attr32 = opp->src[attr->attr].pending;  in mpic_get_attr()
1597 		spin_unlock_irq(&opp->lock);  in mpic_get_attr()
1634 	struct openpic *opp = dev->private;  in mpic_destroy()  local
1637 	kfree(opp);  in mpic_destroy()
1641 static int mpic_set_default_irq_routing(struct openpic *opp)  in mpic_set_default_irq_routing()  argument
1650 	kvm_set_irq_routing(opp->kvm, routing, 0, 0);  in mpic_set_default_irq_routing()
1658 	struct openpic *opp;  in mpic_create()  local
1665 	opp = kzalloc(sizeof(struct openpic), GFP_KERNEL);  in mpic_create()
1666 	if (!opp)  in mpic_create()
1669 	dev->private = opp;  in mpic_create()
1670 	opp->kvm = dev->kvm;  in mpic_create()
1671 	opp->dev = dev;  in mpic_create()
1672 	opp->model = type;  in mpic_create()
1673 	spin_lock_init(&opp->lock);  in mpic_create()
1675 	add_mmio_region(opp, &openpic_gbl_mmio);  in mpic_create()
1676 	add_mmio_region(opp, &openpic_tmr_mmio);  in mpic_create()
1677 	add_mmio_region(opp, &openpic_src_mmio);  in mpic_create()
1678 	add_mmio_region(opp, &openpic_cpu_mmio);  in mpic_create()
1680 	switch (opp->model) {  in mpic_create()
1682 		opp->fsl = &fsl_mpic_20;  in mpic_create()
1683 		opp->brr1 = 0x00400200;  in mpic_create()
1684 		opp->flags |= OPENPIC_FLAG_IDR_CRIT;  in mpic_create()
1685 		opp->nb_irqs = 80;  in mpic_create()
1686 		opp->mpic_mode_mask = GCR_MODE_MIXED;  in mpic_create()
1688 		fsl_common_init(opp);  in mpic_create()
1693 		opp->fsl = &fsl_mpic_42;  in mpic_create()
1694 		opp->brr1 = 0x00400402;  in mpic_create()
1695 		opp->flags |= OPENPIC_FLAG_ILR;  in mpic_create()
1696 		opp->nb_irqs = 196;  in mpic_create()
1697 		opp->mpic_mode_mask = GCR_MODE_PROXY;  in mpic_create()
1699 		fsl_common_init(opp);  in mpic_create()
1708 	ret = mpic_set_default_irq_routing(opp);  in mpic_create()
1712 	openpic_reset(opp);  in mpic_create()
1715 	dev->kvm->arch.mpic = opp;  in mpic_create()
1720 	kfree(opp);  in mpic_create()
1736 	struct openpic *opp = dev->private;  in kvmppc_mpic_connect_vcpu()  local
1741 	if (opp->kvm != vcpu->kvm)  in kvmppc_mpic_connect_vcpu()
1746 	spin_lock_irq(&opp->lock);  in kvmppc_mpic_connect_vcpu()
1748 	if (opp->dst[cpu].vcpu) {  in kvmppc_mpic_connect_vcpu()
1757 	opp->dst[cpu].vcpu = vcpu;  in kvmppc_mpic_connect_vcpu()
1758 	opp->nb_cpus = max(opp->nb_cpus, cpu + 1);  in kvmppc_mpic_connect_vcpu()
1760 	vcpu->arch.mpic = opp;  in kvmppc_mpic_connect_vcpu()
1765 	if (opp->mpic_mode_mask == GCR_MODE_PROXY)  in kvmppc_mpic_connect_vcpu()
1769 	spin_unlock_irq(&opp->lock);  in kvmppc_mpic_connect_vcpu()
1778 void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu)  in kvmppc_mpic_disconnect_vcpu()  argument
1780 	BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu);  in kvmppc_mpic_disconnect_vcpu()
1782 	opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL;  in kvmppc_mpic_disconnect_vcpu()
1796 	struct openpic *opp = kvm->arch.mpic;  in mpic_set_irq()  local
1799 	spin_lock_irqsave(&opp->lock, flags);  in mpic_set_irq()
1800 	openpic_set_irq(opp, irq, level);  in mpic_set_irq()
1801 	spin_unlock_irqrestore(&opp->lock, flags);  in mpic_set_irq()
1810 	struct openpic *opp = kvm->arch.mpic;  in kvm_set_msi()  local
1813 	spin_lock_irqsave(&opp->lock, flags);  in kvm_set_msi()
1820 	spin_unlock_irqrestore(&opp->lock, flags);  in kvm_set_msi()