131 } pm_regs;  variable
295 		pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;  in set_pm_event()
303 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
319 	pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
320 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);  in set_pm_event()
321 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);  in set_pm_event()
322 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);  in set_pm_event()
347 		pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);  in set_pm_event()
349 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
355 			pm_regs.debug_bus_control |=  in set_pm_event()
361 					pm_regs.group_control |=  in set_pm_event()
381 	if (pm_regs.pm_cntrl.enable == 1)  in write_pm_cntrl()
384 	if (pm_regs.pm_cntrl.stop_at_max == 1)  in write_pm_cntrl()
387 	if (pm_regs.pm_cntrl.trace_mode != 0)  in write_pm_cntrl()
388 		val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);  in write_pm_cntrl()
390 	if (pm_regs.pm_cntrl.trace_buf_ovflw == 1)  in write_pm_cntrl()
391 		val |= CBE_PM_TRACE_BUF_OVFLW(pm_regs.pm_cntrl.trace_buf_ovflw);  in write_pm_cntrl()
392 	if (pm_regs.pm_cntrl.freeze == 1)  in write_pm_cntrl()
395 	val |= CBE_PM_SPU_ADDR_TRACE_SET(pm_regs.pm_cntrl.spu_addr_trace);  in write_pm_cntrl()
401 	val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);  in write_pm_cntrl()
415 			pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;  in set_count_mode()
417 			pm_regs.pm_cntrl.count_mode =  in set_count_mode()
421 			pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;  in set_count_mode()
423 			pm_regs.pm_cntrl.count_mode =  in set_count_mode()
473 	pm_regs.group_control = 0;  in cell_virtual_cntr()
474 	pm_regs.debug_bus_control = 0;  in cell_virtual_cntr()
539 					   pm_regs.pm07_cntrl);  in cell_virtual_cntr()
666 		enable_ctr(cpu, 0, pm_regs.pm07_cntrl);  in spu_evnt_swap()
716 	pm_regs.pm_cntrl.trace_buf_ovflw = 1;  in cell_reg_setup_spu_events()
722 	pm_regs.pm_cntrl.trace_mode = 2;  in cell_reg_setup_spu_events()
724 	pm_regs.pm_cntrl.spu_addr_trace = 0x1;  /* using debug bus  in cell_reg_setup_spu_events()
851 	pm_regs.group_control = 0;  in cell_reg_setup()
852 	pm_regs.debug_bus_control = 0;  in cell_reg_setup()
853 	pm_regs.pm_cntrl.stop_at_max = 1;  in cell_reg_setup()
854 	pm_regs.pm_cntrl.trace_mode = 0;  in cell_reg_setup()
855 	pm_regs.pm_cntrl.freeze = 1;  in cell_reg_setup()
856 	pm_regs.pm_cntrl.trace_buf_ovflw = 0;  in cell_reg_setup()
857 	pm_regs.pm_cntrl.spu_addr_trace = 0;  in cell_reg_setup()
925 	cbe_write_pm(cpu, group_control, pm_regs.group_control);  in cell_cpu_setup()
926 	cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);  in cell_cpu_setup()
1374 			enable_ctr(cpu, 0, pm_regs.pm07_cntrl);  in cell_global_start_spu_events()
1420 				enable_ctr(cpu, i, pm_regs.pm07_cntrl);  in cell_global_start_ppu()