99 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,  in u3_agp_cfg_access()  argument
104 	if (bus == hose->first_busno) {  in u3_agp_cfg_access()
113 		out_le32(hose->cfg_addr, caddr);  in u3_agp_cfg_access()
114 	} while (in_le32(hose->cfg_addr) != caddr);  in u3_agp_cfg_access()
117 	return hose->cfg_data + offset;  in u3_agp_cfg_access()
123 	struct pci_controller *hose;  in u3_agp_read_config()  local
126 	hose = pci_bus_to_host(bus);  in u3_agp_read_config()
127 	if (hose == NULL)  in u3_agp_read_config()
130 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_read_config()
154 	struct pci_controller *hose;  in u3_agp_write_config()  local
157 	hose = pci_bus_to_host(bus);  in u3_agp_write_config()
158 	if (hose == NULL)  in u3_agp_write_config()
161 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_write_config()
198 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,  in u3_ht_cfg_access()  argument
201 	if (bus == hose->first_busno) {  in u3_ht_cfg_access()
204 		return hose->cfg_data + u3_ht_cfa0(devfn, offset);  in u3_ht_cfg_access()
206 		return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);  in u3_ht_cfg_access()
209 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_read_config()  argument
214 	addr = hose->cfg_addr;  in u3_ht_root_read_config()
232 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_write_config()  argument
237 	addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));  in u3_ht_root_write_config()
260 	struct pci_controller *hose;  in u3_ht_read_config()  local
263 	hose = pci_bus_to_host(bus);  in u3_ht_read_config()
264 	if (hose == NULL)  in u3_ht_read_config()
267 	if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))  in u3_ht_read_config()
268 		return u3_ht_root_read_config(hose, offset, len, val);  in u3_ht_read_config()
273 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_read_config()
298 	struct pci_controller *hose;  in u3_ht_write_config()  local
301 	hose = pci_bus_to_host(bus);  in u3_ht_write_config()
302 	if (hose == NULL)  in u3_ht_write_config()
305 	if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))  in u3_ht_write_config()
306 		return u3_ht_root_write_config(hose, offset, len, val);  in u3_ht_write_config()
311 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_write_config()
355 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,  in u4_pcie_cfg_access()  argument
360         if (bus == hose->first_busno)  in u4_pcie_cfg_access()
367                 out_le32(hose->cfg_addr, caddr);  in u4_pcie_cfg_access()
368         } while (in_le32(hose->cfg_addr) != caddr);  in u4_pcie_cfg_access()
371         return hose->cfg_data + offset;  in u4_pcie_cfg_access()
377         struct pci_controller *hose;  in u4_pcie_read_config()  local
380         hose = pci_bus_to_host(bus);  in u4_pcie_read_config()
381         if (hose == NULL)  in u4_pcie_read_config()
385         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_read_config()
408         struct pci_controller *hose;  in u4_pcie_write_config()  local
411         hose = pci_bus_to_host(bus);  in u4_pcie_write_config()
412         if (hose == NULL)  in u4_pcie_write_config()
416         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_write_config()
443 static void __init setup_u3_agp(struct pci_controller* hose)  in setup_u3_agp()  argument
454 	hose->first_busno = 0xf0;  in setup_u3_agp()
455 	hose->last_busno = 0xff;  in setup_u3_agp()
456 	hose->ops = &u3_agp_pci_ops;  in setup_u3_agp()
457 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u3_agp()
458 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u3_agp()
460 	u3_agp = hose;  in setup_u3_agp()
463 static void __init setup_u4_pcie(struct pci_controller* hose)  in setup_u4_pcie()  argument
468         hose->ops = &u4_pcie_pci_ops;  in setup_u4_pcie()
469         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u4_pcie()
470         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u4_pcie()
472         u4_pcie = hose;  in setup_u4_pcie()
475 static void __init setup_u3_ht(struct pci_controller* hose)  in setup_u3_ht()  argument
477 	hose->ops = &u3_ht_pci_ops;  in setup_u3_ht()
483 	hose->cfg_data = ioremap(0xf2000000, 0x02000000);  in setup_u3_ht()
484 	hose->cfg_addr = ioremap(0xf8070000, 0x1000);  in setup_u3_ht()
486 	hose->first_busno = 0;  in setup_u3_ht()
487 	hose->last_busno = 0xef;  in setup_u3_ht()
489 	u3_ht = hose;  in setup_u3_ht()
495 	struct pci_controller *hose;  in maple_add_bridge()  local
508 	hose = pcibios_alloc_controller(dev);  in maple_add_bridge()
509 	if (hose == NULL)  in maple_add_bridge()
511 	hose->first_busno = bus_range ? bus_range[0] : 0;  in maple_add_bridge()
512 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in maple_add_bridge()
513 	hose->controller_ops = maple_pci_controller_ops;  in maple_add_bridge()
517 		setup_u3_agp(hose);  in maple_add_bridge()
521 		setup_u3_ht(hose);  in maple_add_bridge()
525                 setup_u4_pcie(hose);  in maple_add_bridge()
530 		disp_name, hose->first_busno, hose->last_busno);  in maple_add_bridge()
534 	pci_process_bridge_OF_ranges(hose, dev, primary);  in maple_add_bridge()
540 	isa_bridge_find_early(hose);  in maple_add_bridge()