Lines Matching refs:hose
143 struct pci_controller *hose; in macrisc_cfg_map_bus() local
145 hose = pci_bus_to_host(bus); in macrisc_cfg_map_bus()
146 if (hose == NULL) in macrisc_cfg_map_bus()
149 if (bus->number == hose->first_busno) { in macrisc_cfg_map_bus()
158 out_le32(hose->cfg_addr, caddr); in macrisc_cfg_map_bus()
159 } while (in_le32(hose->cfg_addr) != caddr); in macrisc_cfg_map_bus()
162 return hose->cfg_data + offset; in macrisc_cfg_map_bus()
207 static void __init setup_chaos(struct pci_controller *hose, in setup_chaos() argument
211 hose->ops = &chaos_pci_ops; in setup_chaos()
212 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_chaos()
213 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_chaos()
232 static int u3_ht_skip_device(struct pci_controller *hose, in u3_ht_skip_device() argument
248 busdn = hose->dn; in u3_ht_skip_device()
273 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, in u3_ht_cfg_access() argument
277 if (bus == hose->first_busno) { in u3_ht_cfg_access()
279 return hose->cfg_data + U3_HT_CFA0(devfn, offset); in u3_ht_cfg_access()
281 return ((void __iomem *)hose->cfg_addr) + (offset << 2); in u3_ht_cfg_access()
283 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); in u3_ht_cfg_access()
289 struct pci_controller *hose; in u3_ht_read_config() local
293 hose = pci_bus_to_host(bus); in u3_ht_read_config()
294 if (hose == NULL) in u3_ht_read_config()
298 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_read_config()
302 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_read_config()
340 struct pci_controller *hose; in u3_ht_write_config() local
344 hose = pci_bus_to_host(bus); in u3_ht_write_config()
345 if (hose == NULL) in u3_ht_write_config()
349 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_write_config()
353 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_write_config()
403 struct pci_controller *hose; in u4_pcie_cfg_map_bus() local
409 hose = pci_bus_to_host(bus); in u4_pcie_cfg_map_bus()
410 if (!hose) in u4_pcie_cfg_map_bus()
413 if (bus->number == hose->first_busno) { in u4_pcie_cfg_map_bus()
420 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_map_bus()
421 } while (in_le32(hose->cfg_addr) != caddr); in u4_pcie_cfg_map_bus()
424 return hose->cfg_data + offset; in u4_pcie_cfg_map_bus()
497 struct pci_controller* hose; in init_p2pbridge() local
515 hose = pci_find_hose_for_OF_device(p2pbridge); in init_p2pbridge()
516 if (!hose) { in init_p2pbridge()
520 if (early_read_config_word(hose, bus, devfn, in init_p2pbridge()
527 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); in init_p2pbridge()
545 struct pci_controller* hose = in init_second_ohare() local
547 if (!hose) { in init_second_ohare()
552 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); in init_second_ohare()
555 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); in init_second_ohare()
572 struct pci_controller *hose; in fixup_nec_usb2() local
594 hose = pci_find_hose_for_OF_device(nec); in fixup_nec_usb2()
595 if (!hose) in fixup_nec_usb2()
597 early_read_config_dword(hose, bus, devfn, 0xe4, &data); in fixup_nec_usb2()
602 early_write_config_dword(hose, bus, devfn, 0xe4, data); in fixup_nec_usb2()
607 static void __init setup_bandit(struct pci_controller *hose, in setup_bandit() argument
610 hose->ops = ¯isc_pci_ops; in setup_bandit()
611 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_bandit()
612 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_bandit()
613 init_bandit(hose); in setup_bandit()
616 static int __init setup_uninorth(struct pci_controller *hose, in setup_uninorth() argument
621 hose->ops = ¯isc_pci_ops; in setup_uninorth()
622 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_uninorth()
623 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_uninorth()
630 static void __init setup_u3_agp(struct pci_controller* hose) in setup_u3_agp() argument
641 hose->first_busno = 0xf0; in setup_u3_agp()
642 hose->last_busno = 0xff; in setup_u3_agp()
644 hose->ops = ¯isc_pci_ops; in setup_u3_agp()
645 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u3_agp()
646 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u3_agp()
647 u3_agp = hose; in setup_u3_agp()
650 static void __init setup_u4_pcie(struct pci_controller* hose) in setup_u4_pcie() argument
655 hose->ops = &u4_pcie_pci_ops; in setup_u4_pcie()
656 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u4_pcie()
657 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u4_pcie()
665 hose->first_busno = 0x00; in setup_u4_pcie()
666 hose->last_busno = 0xff; in setup_u4_pcie()
669 static void __init parse_region_decode(struct pci_controller *hose, in parse_region_decode() argument
693 hose->mem_resources[cur].flags = IORESOURCE_MEM; in parse_region_decode()
694 hose->mem_resources[cur].name = hose->dn->full_name; in parse_region_decode()
695 hose->mem_resources[cur].start = base; in parse_region_decode()
696 hose->mem_resources[cur].end = end; in parse_region_decode()
697 hose->mem_offset[cur] = 0; in parse_region_decode()
701 hose->mem_resources[cur].end = end; in parse_region_decode()
707 static void __init setup_u3_ht(struct pci_controller* hose) in setup_u3_ht() argument
709 struct device_node *np = hose->dn; in setup_u3_ht()
713 hose->ops = &u3_ht_pci_ops; in setup_u3_ht()
726 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); in setup_u3_ht()
727 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); in setup_u3_ht()
734 hose->io_base_phys = 0xf4000000; in setup_u3_ht()
735 hose->pci_io_size = 0x00400000; in setup_u3_ht()
736 hose->io_resource.name = np->full_name; in setup_u3_ht()
737 hose->io_resource.start = 0; in setup_u3_ht()
738 hose->io_resource.end = 0x003fffff; in setup_u3_ht()
739 hose->io_resource.flags = IORESOURCE_IO; in setup_u3_ht()
740 hose->first_busno = 0; in setup_u3_ht()
741 hose->last_busno = 0xef; in setup_u3_ht()
744 decode = in_be32(hose->cfg_addr + 0x80); in setup_u3_ht()
768 parse_region_decode(hose, decode); in setup_u3_ht()
780 struct pci_controller *hose; in pmac_add_bridge() local
798 hose = pcibios_alloc_controller(dev); in pmac_add_bridge()
799 if (!hose) in pmac_add_bridge()
801 hose->first_busno = bus_range ? bus_range[0] : 0; in pmac_add_bridge()
802 hose->last_busno = bus_range ? bus_range[1] : 0xff; in pmac_add_bridge()
803 hose->controller_ops = pmac_pci_controller_ops; in pmac_add_bridge()
810 setup_u3_agp(hose); in pmac_add_bridge()
814 setup_u3_ht(hose); in pmac_add_bridge()
818 setup_u4_pcie(hose); in pmac_add_bridge()
823 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); in pmac_add_bridge()
829 primary = setup_uninorth(hose, &rsrc); in pmac_add_bridge()
833 setup_grackle(hose); in pmac_add_bridge()
836 setup_bandit(hose, &rsrc); in pmac_add_bridge()
839 setup_chaos(hose, &rsrc); in pmac_add_bridge()
845 disp_name, (unsigned long long)rsrc.start, hose->first_busno, in pmac_add_bridge()
846 hose->last_busno); in pmac_add_bridge()
850 hose, hose->cfg_addr, hose->cfg_data); in pmac_add_bridge()
854 pci_process_bridge_OF_ranges(hose, dev, primary); in pmac_add_bridge()