508 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)  in ipic_read()  function
532 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_unmask_irq()
548 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq()
587 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq_and_ack()
645 	vold = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_set_irq_type()
750 	temp = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_init()
784 	temp = ipic_read(ipic->regs, ipic_info[src].prio);  in ipic_set_priority()
805 	temp = ipic_read(ipic->regs, IPIC_SICFR);  in ipic_set_highest_priority()
829 	temp = ipic_read(ipic->regs, IPIC_SERMR);  in ipic_enable_mcp()
839 	temp = ipic_read(ipic->regs, IPIC_SERMR);  in ipic_disable_mcp()
846 	return ipic_read(primary_ipic->regs, IPIC_SERMR);  in ipic_get_mcp_status()
862 	irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;  in ipic_get_irq()
887 	ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);  in ipic_suspend()
888 	ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);  in ipic_suspend()
889 	ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);  in ipic_suspend()
890 	ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);  in ipic_suspend()
891 	ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);  in ipic_suspend()
892 	ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);  in ipic_suspend()
893 	ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);  in ipic_suspend()
894 	ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);  in ipic_suspend()
895 	ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_suspend()
896 	ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_suspend()
897 	ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);  in ipic_suspend()
898 	ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);  in ipic_suspend()