57 #define REG_W0		(__MAX_BPF_REG+0)	/* Work register 1 (even) */  macro
62 #define REG_0		REG_W0			/* Register 0 */
88 	[REG_W0]	= 0,
580 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
588 		EMIT4_IMM(0xa7080000, REG_W0, 0);  in bpf_jit_insn()
592 		EMIT4(0xb9970000, REG_W0, src_reg);  in bpf_jit_insn()
600 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
608 		EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
612 		EMIT4(0xb9870000, REG_W0, src_reg);  in bpf_jit_insn()
620 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
629 		EMIT4_IMM(0xa7080000, REG_W0, 0);  in bpf_jit_insn()
633 		EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,  in bpf_jit_insn()
642 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
651 		EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
655 		EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,  in bpf_jit_insn()
869 		EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);  in bpf_jit_insn()
871 		EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
876 		EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);  in bpf_jit_insn()
878 		EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
883 		EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);  in bpf_jit_insn()
885 		EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
890 		EMIT6_IMM(0xc0010000, REG_W0, imm);  in bpf_jit_insn()
892 		EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);  in bpf_jit_insn()
900 		EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,  in bpf_jit_insn()
906 		EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,  in bpf_jit_insn()