58 #define REG_W1		(__MAX_BPF_REG+1)	/* Work register 2 (odd) */  macro
89 	[REG_W1]	= 1,
389 			EMIT4(0xb9040000, REG_W1, REG_15);  in bpf_jit_prologue()
396 			EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,  in bpf_jit_prologue()
406 		EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,  in bpf_jit_prologue()
409 		EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,  in bpf_jit_prologue()
412 		EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,  in bpf_jit_prologue()
580 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
590 		EMIT2(0x1800, REG_W1, dst_reg);  in bpf_jit_insn()
600 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
610 		EMIT4(0xb9040000, REG_W1, dst_reg);  in bpf_jit_insn()
620 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
631 		EMIT2(0x1800, REG_W1, dst_reg);  in bpf_jit_insn()
642 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
653 		EMIT4(0xb9040000, REG_W1, dst_reg);  in bpf_jit_insn()
946 		EMIT6_DISP(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,  in bpf_jit_insn()
949 		EMIT2(0x0d00, REG_14, REG_W1);  in bpf_jit_insn()
1005 		EMIT6_IMM(0xc0010000, REG_W1, imm);  in bpf_jit_insn()
1007 		EMIT4(0xb9800000, REG_W1, dst_reg);  in bpf_jit_insn()
1031 		EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);  in bpf_jit_insn()
1035 		EMIT6_IMM(0xc0010000, REG_W1, imm);  in bpf_jit_insn()
1037 		EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);  in bpf_jit_insn()
1041 		EMIT6_IMM(0xc0010000, REG_W1, imm);  in bpf_jit_insn()
1043 		EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);  in bpf_jit_insn()
1102 		EMIT6_IMM(0xc00f0000, REG_W1, func_addr);  in bpf_jit_insn()
1111 		EMIT2(0x0d00, BPF_REG_5, REG_W1);  in bpf_jit_insn()