17 #define PPC_CCBR(idx)	(0xff200800 + (sizeof(u32) * idx))  argument
18 #define PPC_PMCTR(idx)	(0xfc100000 + (sizeof(u32) * idx))  argument
230 static u64 sh4a_pmu_read(int idx)  in sh4a_pmu_read()  argument
232 	return __raw_readl(PPC_PMCTR(idx));  in sh4a_pmu_read()
235 static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)  in sh4a_pmu_disable()  argument
239 	tmp = __raw_readl(PPC_CCBR(idx));  in sh4a_pmu_disable()
241 	__raw_writel(tmp, PPC_CCBR(idx));  in sh4a_pmu_disable()
244 static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)  in sh4a_pmu_enable()  argument
250 	tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;  in sh4a_pmu_enable()
253 	tmp = __raw_readl(PPC_CCBR(idx));  in sh4a_pmu_enable()
255 	__raw_writel(tmp, PPC_CCBR(idx));  in sh4a_pmu_enable()
257 	__raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));  in sh4a_pmu_enable()