180 				   struct hw_perf_event *hwc, int idx)  in sh_perf_event_update()  argument
200 	new_raw_count = sh_pmu->read(idx);  in sh_perf_event_update()
224 	int idx = hwc->idx;  in sh_pmu_stop()  local
227 		sh_pmu->disable(hwc, idx);  in sh_pmu_stop()
228 		cpuc->events[idx] = NULL;  in sh_pmu_stop()
233 		sh_perf_event_update(event, &event->hw, idx);  in sh_pmu_stop()
242 	int idx = hwc->idx;  in sh_pmu_start()  local
244 	if (WARN_ON_ONCE(idx == -1))  in sh_pmu_start()
250 	cpuc->events[idx] = event;  in sh_pmu_start()
252 	sh_pmu->enable(hwc, idx);  in sh_pmu_start()
260 	__clear_bit(event->hw.idx, cpuc->used_mask);  in sh_pmu_del()
269 	int idx = hwc->idx;  in sh_pmu_add()  local
274 	if (__test_and_set_bit(idx, cpuc->used_mask)) {  in sh_pmu_add()
275 		idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);  in sh_pmu_add()
276 		if (idx == sh_pmu->num_events)  in sh_pmu_add()
279 		__set_bit(idx, cpuc->used_mask);  in sh_pmu_add()
280 		hwc->idx = idx;  in sh_pmu_add()
283 	sh_pmu->disable(hwc, idx);  in sh_pmu_add()
298 	sh_perf_event_update(event, &event->hw, event->hw.idx);  in sh_pmu_read()